ddr mode definition.
Module Instance | Base Address | Register Address |
---|---|---|
i_noc_mpu_m0_ddr_T_main_Scheduler | 0xFFD12400 | 0xFFD12410 |
Offset: 0x10
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
BWRATIOEXTENDED RW 0x0 |
AUTOPRECHARGE RW 0x0 |
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
1 | BWRATIOEXTENDED | When set to one, four DRAM clock cycles (8 DDR transfers) are used to transfer each word of data. When set to one, the BwRatio field of the DdrTiming register must be set to zero. |
RW | 0x0 |
0 | AUTOPRECHARGE | When set to one, pages are automatically closed after each access, when set to zero, pages are left opened until an access in a different page occurs. |
RW | 0x0 |