Module Instance | Base Address | Register Address |
---|---|---|
i_io48_hmc_mmr_io48_mmr | 0xFFCFA000 | 0xFFCFA030 |
Offset: 0x30
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
cfg_dbc3_pipe_lat 0x0 |
cfg_dbc2_pipe_lat 0x0 |
cfg_dbc1_pipe_lat 0x0 |
cfg_dbc0_pipe_lat 0x0 |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
cfg_dbc0_pipe_lat 0x0 |
cfg_dbc2ctrl_sel 0x0 |
cfg_dbc3_ctrl_sel 0x0 |
cfg_dbc2_ctrl_sel 0x0 |
cfg_dbc1_ctrl_sel 0x0 |
cfg_dbc0_ctrl_sel 0x0 |
cfg_ctrl2dbc_switch1 0x0 |
cfg_ctrl2dbc_switch0 0x0 |
cfg_dbc3_output_regd 0x0 |
cfg_dbc2_output_regd 0x0 |
cfg_dbc1_output_regd 0x0 |
cfg_dbc0_output_regd 0x0 |
cfg_ctrl_output_regd 0x0 |
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
26:24 | cfg_dbc3_pipe_lat | Specifies in number of controller clock cycles the latency of pipelining the signals from control path to DBC3 |
RW | 0x0 |
23:21 | cfg_dbc2_pipe_lat | Specifies in number of controller clock cycles the latency of pipelining the signals from control path to DBC2 |
RW | 0x0 |
20:18 | cfg_dbc1_pipe_lat | Specifies in number of controller clock cycles the latency of pipelining the signals from control path to DBC1 |
RW | 0x0 |
17:15 | cfg_dbc0_pipe_lat | Specifies in number of controller clock cycles the latency of pipelining the signals from control path to DBC0 |
RW | 0x0 |
14:13 | cfg_dbc2ctrl_sel | Specifies which DBC is driven by the local control path. 2 |
RW | 0x0 |
12 | cfg_dbc3_ctrl_sel | DBC3 - control path select. 1 |
RW | 0x0 |
11 | cfg_dbc2_ctrl_sel | DBC2 - control path select. 1 |
RW | 0x0 |
10 | cfg_dbc1_ctrl_sel | DBC1 - control path select. 1 |
RW | 0x0 |
9 | cfg_dbc0_ctrl_sel | DBC0 - control path select. 1 |
RW | 0x0 |
8:7 | cfg_ctrl2dbc_switch1 | Select of the MUX ctrl2dbc_switch1. 2 |
RW | 0x0 |
6:5 | cfg_ctrl2dbc_switch0 | Select of the MUX ctrl2dbc_switch0. 2 |
RW | 0x0 |
4 | cfg_dbc3_output_regd | Set to one to register the HMC command output. Set to 0 to disable it. |
RW | 0x0 |
3 | cfg_dbc2_output_regd | Set to one to register the HMC command output. Set to 0 to disable it. |
RW | 0x0 |
2 | cfg_dbc1_output_regd | Set to one to register the HMC command output. Set to 0 to disable it. |
RW | 0x0 |
1 | cfg_dbc0_output_regd | Set to one to register the HMC command output. Set to 0 to disable it. |
RW | 0x0 |
0 | cfg_ctrl_output_regd | Set to one to register the HMC command output. Set to 0 to disable it. |
RW | 0x0 |