counter0mask

         
      
Module Instance Base Address Register Address
i_io48_hmc_mmr_io48_mmr 0xFFCFA000 0xFFCFA100

Offset: 0x100

Access: RW

Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

counter_zero_mask

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

counter_zero_mask

0x0

counter0mask Fields

Bit Name Description Access Reset
31:0 counter_zero_mask
Performance monitoring register. This register is used to mask off the internal signals selected by the debug select byte to either examine a bit (and expect it to be a one or a zero) or to ignore the bit.
RW 0x0