Register 11 (AHB or AXI Status Register)
This register provides the active status of the AHB master interface or AXI interface's read and write channels. This register is present and valid only in the GMAC-AHB and GMAC-AXI configurations. This register is useful for debugging purposes. In addition, this register is valid only in the Channel 0 DMA when multiple channels are present in the AV mode.
Module Instance | Base Address | Register Address |
---|---|---|
i_emac_emac0 | 0xFF800000 | 0xFF80102C |
i_emac_emac1 | 0xFF802000 | 0xFF80302C |
i_emac_emac2 | 0xFF804000 | 0xFF80502C |
Offset: 0x102C
Access: RO
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
reserved_31_2 RO 0x0 |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
reserved_31_2 RO 0x0 |
axirdsts RO 0x0 |
axwhsts RO 0x0 |
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
31:2 | reserved_31_2 | Reserved |
RO | 0x0 |
1 | axirdsts | AXI Master Read Channel Status When high, it indicates that AXI Master's read channel is active and transferring data. |
RO | 0x0 |
0 | axwhsts | AXI Master Write Channel or AHB Master Status When high, it indicates that AXI Master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, it indicates that the AHB master interface FSMs are in the non-idle state. |
RO | 0x0 |