DDR IO Control Register
Module Instance | Base Address | Register Address |
---|---|---|
ecc_hmc_ocp_slv_block | 0xFFCFB000 | 0xFFCFB008 |
Offset: 0x8
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
IO_SIZE 0x0 |
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
1:0 | IO_SIZE | External Configuration of DDR IO size. This field indicates the width of the external DDR to which the hard memory cotnroller is interfacing. These bits are configured at the start to indicate the external DDRIO size. 0x0 = DDR IO x16. default value after reset 0x1 = DDR IO x32 0x2 = DDR IO x64 |
RW | 0x0 |