4 4.1 IC Package Electrical Characteristics As microprocessor speeds have increased and power supply voltages have decreased, the function of the microprocessor package has transitioned from that of a mechanical interconnect which provides protection for the die from the outside environment to that of an electrical interconnect that affects microprocessor performance and ...which must be properly understood in an electrical context. Inherent in understanding the electrical performance effects of the package is the need for electrical characterization of the package. The package is a complex electrical environment and the characterization of this environment is a multi-faceted task that consists of models constructed from both theoretical calculations and experimental measurements. In simple terms, a package electrical model translates the physical properties of a package into electrical characteristics that are usually combined into a circuit representation. The typical electrical circuit characteristics that are reported are DC resistance (R), inductance (L), capacitance (C), and characteristic impedance (Z_o) of various structures in the package. A package model consists of two parts, both of which are necessary for fully understanding the electrical performance effects of the package environment on Intel’s microprocessors. The first is an I/O lead model that describes the signal path from the die to the board. Depending upon the complexity of the model required for simulation purposes, the I/O lead model can take the form of a simple lumped circuit model, a distributed lumped circuit model, a single-conductor transmission-line model, or a multiple-conductor transmission-line model. While lumped models can adequately model simple effects, such as DC resistive voltage drop, more sophisticated models like the multiple-conductor transmission-line model include effects such as time delay and crosstalk. The second part of a package model is a power-distribution network that describes the power scheme of the package. Like the I/O lead model, the sophistication of the power-distribution network can vary from a simple distributed lumped model to a complex circuit network called a PEEC (partial-element equivalent circuit) network. The simpler models can describe gross electrical characteristics of the power-distribution network, such as DC resistive drop for the entire package, whereas the more complex models enable the analysis of the effects of the power- distribution topology. Experimental characterization of the package can include measurements of trace characteristics and power loop parasitics, to name a few of the package aspects that can be characterized. Experimental characterization is usually the final, validation stage of the package-design process. Care must be taken in determining the characteristics that are measured. If a comparison between measured and modeled data is to be made, then the same assumptions used in obtaining the theoretical package model must be replicated in the test environment. The following sections provide an overview of basic package modeling terminology and methodology, an overview of experimental characterization, and modeled data for the packages that Intel uses for its most advanced microprocessors. These products are housed in packages representative of a broad spectrum of package technologies, including CPGA (ceramic pin-grid array), PPGA (plastic pin-grid array), H-PBGA (high thermal plastic ball grid array), TCP (tape carrier package), OLGA (organic land-grid array), and FC-PGA (flip-chip pin-grid array). For the 2000 Packaging Databook 4-1 Performance Characteristics of IC Packages sake of completeness, package parasitics data for older Read the full Performance Characteristics of IC Packages.