Intel® Stratix® 10 SoCs, manufactured on Intel’s 14 nm process technology, combine a quad-core ARM* Cortex*–A53 MPCore* hard processor system with the revolutionary Intel® Hyperflex™ FPGA Architecture to deliver breakthrough advantages in performance, power efficiency, density, and system integration. Intel® Stratix® 10 devices deliver 2X core performance gains over previous-generation, high-performance FPGAs with up to 70% lower power.1

Family Variants

All Intel® Stratix® 10 SoC Variants

Learn more about all device variations and how specifications compare.

View overview table

Benefits

By integrating the FPGA and the ARM* processor, Intel® Stratix® 10 SoCs provide an ideal solution for 5G wireless communication, software-defined radios, secure computing for military applications, network function virtualization (NFV), and data center acceleration.

Designed for Productivity

Design productivity is one of the driving philosophies of the Intel® Stratix® 10 SoC architecture. Intel® Stratix® 10 SoCs offer full software compatibility with previous-generation SoCs, a broad eco-system of ARM* software and tools, and the enhanced FPGA and digital signal processing (DSP) hardware design flow.

  • Extensive eco-system of ARM for software development 
  • Software-compatibility between 28 nm Cyclone® V and Arria® V SoCs and 20 nm Intel® Arria® 10 SoCs
  • Intel® Quartus® Prime Software featuring:
    • High-level automated design flow with Open Computing Language (OpenCL™) compiler
    • Model-based DSP hardware design with the DSP Builder for Intel® FPGAs
  • Intel® Stratix® 10 SoC Virtual Platform to enable early software development and verification

   

Achieve Performance Breakthroughs

Break Through the Bandwidth Barrier

  • Up to 144 transceivers with data rates up to 30 Gbps deliver 4X serial transceiver bandwidth from previous-generation FPGAs for high port count designs
    • 30 Gbps backplane capability for versatile data switching applications
    • A path to 56 Gbps chip-to-chip/module capability for leading-edge interface standards
  • Over 2.5 Tbps bandwidth for serial memory with support for Hybrid Memory Cube
  • Over 2.3 Tbps bandwidth for parallel memory interfaces with support for DDR4 SDRAM at 2,666 Mbps

Lower Operating Expense

  • Quad-core ARM* Cortex*-A53 processor optimized for performance per watt
  • Leveraging Intel's leadership in process technology, Intel® Stratix® 10 devices offer the most power-efficient technologies
    • Up to 70% lower power than prior-generation high-end SoCs
    • Up to 80 GFLOPS/Watt of single-precision floating-point power efficiency

Achieve High Levels of System Integration

  • 64-bit quad-core ARM Cortex-A53 processor to enable hardware virtualization, system management and monitoring capabilities, acceleration pre-processing, and more
  • Highest density FPGA fabric with 5.5M logic elements in a monolithic implementation
  • Heterogeneous 3D SiP solutions including transceivers and other advanced components

Achieve high designer productivity with optimized FPGA and SoC design software

  • Heterogeneous debug, profiling, and whole chip visualization with Intel® FPGA SoC FPGA Embedded Development Suite (EDS) featuring the ARM* Development Studio 5* (DS-5*) Intel® SoC FPGA Edition Toolkit
  • New engine optimized for multi-million logic elements (LE) FPGA designs providing
    • Up to 8X faster compile times
    • Significant reduction in design iterations
    • Hyper-Aware design flow to optimize designs for the Intel® Hyperflex™ FPGA Architecture
  • C-based design entry using the Intel® FPGA SDK for OpenCL™, offering a design environment that is easy to implement on SoC FPGAs2
  • Heterogeneous C-based modeling and hardware design with the Intel® FPGA SDK for OpenCL™

Get Faster Time to Market

  • Start designing with Intel® Arria® 10 SoC and migrate to Intel® Stratix® 10 SoC
    • Code compatibility with previous-generation SoCs
    • Cortex-A53 processor supports 32-bit execution mode
  • Complementary Intel® Enpirion® PowerSoCs offer complete and validated power solution for Intel® Stratix® 10 SoCs with higher performance, lower system power, higher reliability, smaller footprint, and faster time to market

Obtain comprehensive high-performance FPGA security capabilities

  • Integrated Secure Device Manager (SDM) for flexibility to update configuration code
  • Multi-factor authentication
  • Physically Unclonable Function (PUF)

 

Features

The Intel® Stratix® 10 SoCs HPS architecture now includes a System Memory Management Unit, which enables hardware virtualization across the processor and FPGA domains. Intel® Stratix® 10 SoCs add a Cache Coherency Unit to provide one-way (I/O) cache coherency with the ARM* Cortex*–A53 MPCore* processor. Intel® Stratix® 10 SoCs also include up to 10 TFLOPS of hardened floating-point digital signal processing (DSP) blocks, embedded high-speed transceivers, hard memory controllers, and protocol intellectual property (IP) controllers - all in a single, highly integrated package.

 

Intel® Stratix® 10 SoCs that are manufactured on Intel’s 14 nm FinFET process technology, feature our third-generation hard processor system (HPS) based on a quad-core ARM* Cortex*–A53 MPCore* processor cluster. The hard processor system also includes a deep feature set of peripherals and is combined with the ground-breaking Intel® Hyperflex™ FPGA Architecture to create the industry's highest performance SoC FPGA product family.

Intel® Stratix® 10 SoC Block Diagram

HPS: Quad-core ARM* Cortex*-A53 Hard Processor System
SDM: Secure Device Manager
EMIB: Embedded Multi-Die Interconnect Bridge

Feature

Description

Processor

Quad-core ARM* Cortex*–A53 MPCore* processor cluster up to 1.5 GHz

Coprocessors

Vector floating-point unit (VFPU) single and double precision, ARM* Neon* media processing engine for each processor

Level 1 Cache

32 KB L1 instruction cache with parity, 32 KB L1 data cache with error correction code (ECC)

Level 2 Cache

1 MB KB shared L2 cache with ECC

On-Chip Memory

256 KB on-chip RAM

System Memory Management Unit

System Memory Management Unit enables a unified memory model and extends hardware virtualization into peripherals implemented in the FPGA fabric

Cache Coherency Unit

Provides one-way (I/O) coherency that allows a CCU master to view the coherent memory of the ARM* Cortex*–A53 MPCore* CPUs.

Direct Memory Access (DMA) Controller

8-channel direct memory access (DMA)

Ethernet Media Access Controller (EMAC)

3X 10/100/1000 EMAC with integrated DMA

USB On-The-Go Controller (OTG)

2X USB OTG with integrated DMA

UART Controller

2X UART 16550 compatible

Serial Peripheral Interface (SPI) Controller

4X SPI

I2C Controller

5X I2C

SD/SDIO/MMC Controller

1X eMMC 4.5 with DMA and CE-ATA support

NAND Flash Controller

1X ONFI 1.0 or later 8 and 16-bit support

General-Purpose I/O (GPIO)

Maximum 48 software-programmable GPIO

Timers 4X general-purpose timers, 4X watchdog timers
System Manager Contains memory-mapped control and status registers and logic to control system-level functions and other HPS modules.
Reset Manager Resets signals based on reset requests from sources in the HPS and FPGA fabric, and software writing to the module reset control registers.
Clock Manager Provides software-programmable clock control to configure all clocks generated in the HPS.

Design Tools

Browse through the development tools available for building software and creating FPGA designs for Intel® SoC FPGAs.

Ecosystem

Intel® SoC FPGAs are ARM* processor-based and inherit the strength of the ARM* eco-system. Intel, our ecosystem partners, and the Intel® SoC FPGA user community provide a wide range of options to meet your SoC FPGA development needs.

Videos

Intel® Stratix® 10 Device Demo Videos

28G Transceivers

In this video, we look at the unique transceiver architecture of Intel® Stratix® 10 FPGAs. See H-Tile transceivers that are connected via Intel's EMIB technology and operating at 28 Gbps backplane performance.

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Intel® Hyperflex™ FPGA Architecture

Intel® Hyperflex™ FPGA Architecture in Intel® Stratix® 10 devices provides 2X the Fmax performance.1 This video shows a side-by-side comparison of an original design and a Hyper-Optimized design.

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PCIe* Gen3 DMA to DDR4 SDRAM

Intel® Stratix® 10 devices, which include PCI Express* (PCIe*) and memory controller hard intellectual property (IP) blocks, combined with Avalon® Memory Mapped and direct memory access (DMA) functions to create a high-performance reference design.

Watch video

Documentation and Support


Find technical documentation, videos, and training courses for your Intel® Stratix® 10 SoC FPGA designs.

Информация о продукте и производительности

1

Comparison based on Stratix® V vs. Intel® Stratix® 10 using Intel® Quartus® Prime Pro 16.1 Early Beta. Stratix® V Designs were optimized using 3 step optimization process of Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization in order to utilize Intel® Stratix® 10 architecture enhancements of distributed registers in core fabric. Designs were analyzed using Intel® Quartus® Prime Pro Fast Forward Compile performance exploration tool. For more details, refer to Intel® Hyperflex™ FPGA Architecture Overview White Paper: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01220-hyperflex-architecture-fpga-socs.pdf. Actual performance users will achieve varies based on level of design optimization applied. Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.ru/benchmarks.

2

OpenCL™ and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.