• Intel^® Stratix^® 10 GX devices deliver up to 1 GHz core fabric performance and contain up to 2.8 million LEs in a monolithic fabric. They also feature up to 96 general purpose transceivers on separate transceiver tiles, and 2666 Mbps DDR4 external memory interface performance. The transceivers are capable of up to 28.3 Gbps short reach and across the backplane. These devices are optimized for FPGA applications that require the highest transceiver bandwidth and core fabric performance, with the power efficiency of Intel’s 14 nm tri-gate process technology.
• Intel^® Stratix^® 10 SX devices have a feature set that is identical to Intel^® Stratix^® 10 GX devices, with the addition of an embedded quad-core 64 bit Arm* Cortex* A53 hard processor system.

Common to all Intel^® Stratix^® 10 family variants is a high-performance fabric based on the new Intel^® Hyperflex™ core architecture that includes additional Hyper-Registers throughout the interconnect routing and at the inputs of all functional blocks. The core fabric also contains an enhanced logic array utilizing Intel’s adaptive logic module (ALM) and a rich set of high performance building blocks including:

• M20K (20 Kb) embedded memory blocks
• Variable precision DSP blocks with hard IEEE 754 compliant floating-point units
• Fractional synthesis and integer PLLs
• Hard memory controllers and PHY for external memory interfaces
• General purpose IO cells

To clock these building blocks, Intel^® Stratix^® 10 devices use programmable clock tree synthesis, which uses dedicated clock tree routing to synthesize only those branches of the clock trees required for the application. All devices support in-system, fine-grained partial reconfiguration of the logic array, allowing logic to be added and subtracted from the system while it is operating.

All family variants also contain high speed serial transceivers, containing both the physical medium attachment (PMA) and the physical coding sublayer (PCS), which can be used to implement a variety of industry standard and proprietary protocols. In addition to the hard PCS, Intel^® Stratix^® 10 devices contain multiple instantiations of PCI Express* hard IP that supports Gen1/Gen2/Gen3 rates in x1/x2/x4/x8/x16 lane configurations, and hard 10GBASE-KR/40GBASE-KR4 FEC for every transceiver. The hard PCS, FEC, and PCI Express IP free up valuable core logic resources, save power, and increase your productivity.

Intel^® Stratix^® 10 FPGAs and SoCs deliver many significant improvements over the previous generation high-performance Stratix^® V FPGAs.

These innovations result in the following improvements:

• Improved Core Logic Performance: The Intel^® Hyperflex™ core architecture combined with 14 nm Intel tri-gate technology allows Intel^® Stratix^® 10 devices to achieve 2X the core performance compared to the previous generation
• Lower Power:  Intel^® Stratix^® 10 devices use up to 70% lower power compared to the previous generation, enabled by 14 nm Intel tri-gate technology, the Intel^® Hyperflex™ core architecture, and optional power saving features built into the architecture
• Higher Density: Intel^® Stratix^® 10 devices offer three times the level of integration, with up to 2,800K logic elements (LEs) in a monolithic fabric, over 229 Mbits of embedded memory blocks (M20K), and 11,520 18x19 multipliers
• Embedded Processing: Intel^® Stratix^® 10 SoCs feature a Quad-Core 64 bit Arm* Cortex* -A53 processor optimized for power efficiency and software compatible with previous generation Arria^® and Cyclone^® SoC devices
• Improved Transceiver Performance: With up to 96 transceiver channels implemented in heterogeneous 3D SiP transceiver tiles, Intel^® Stratix^® 10 GX and SX devices support data rates up to 28.3 Gbps chip-to-chip and 28.3 Gbps across the backplane with signal conditioning circuits capable of equalizing over 30 dB of system loss
• Improved DSP Performance: The variable precision DSP block in Intel^® Stratix^® 10 devices features hard fixed and floating point capability, with up to 10 TFLOP IEEE754 single-precision floating point performance
• Additional Hard IP: Intel^® Stratix^® 10 devices include many more hard IP blocks than previous generation devices, with a hard memory controller included in each bank of 48 general purpose IOs, a hard PCIe* Gen3 x16 full protocol stack in each transceiver tile, and a hard 10GBASE-KR/40GBASE-KR4 FEC in every transceiver channel
• Enhanced Core Clocking: Intel^® Stratix^® 10 devices feature programmable clock tree synthesis; clock trees are only synthesized where needed, increasing the flexibility and reducing the power dissipation of the clocking solution
• Additional Core PLLs: The core fabric in Intel^® Stratix^® 10 devices is supported by both integer IO PLLs and fractional synthesis fPLLs, resulting in a greater total number of PLLs available than the previous generation

Intel^® Stratix^® 10 devices offer up to 96 total full-duplex transceiver channels. These channels provide continuous data rates from 1 Gbps to 28.3 Gbps for chip-to-chip, chip-to-module, and backplane applications. In each device,two thirds of the transceivers can be configured up to the maximum data rate of 28.3 Gbps to drive 100G interfaces and C form-factor pluggable CFP2/CFP4 optical modules. For longer-reach backplane driving applications, advanced adaptive equalization circuits are used to equalize over 30 dB of system loss.

All transceiver channels feature a dedicated Physical Medium Attachment (PMA) and a hardened Physical Coding Sublayer (PCS).

• The PMA provides primary interfacing capabilities to physical channels.
• The PCS typically handles encoding/decoding, word alignment, and other pre-processing functions before transferring data to the FPGA core fabric.

Within each transceiver tile, the transceivers are arranged in four banks of six PMA-PCS groups. A wide variety of bonded and non-bonded data rate configurations are possible within each bank, and within each tile, using a highly configurable clock distribution network.

Intel^® Stratix^® 10 device features provide exceptional signal integrity at data rates up to 28.3 Gbps. Clocking options include ultra-low jitter LC tank-based (ATX) PLLs with optional fractional synthesis capability, channel PLLs operating as clock multiplier units (CMUs), and fractional synthesis PLLs (fPLLs).

• ATX PLL—can be configured in integer mode, or optionally, in a new fractional synthesis mode. Each ATX PLL spans the full frequency range of the supported data rate range providing a stable, flexible clock source with the lowest jitter.
• CMU PLL—when not being used as a transceiver, select PMA channels can be configured as channel PLLs operating as CMUs to provide an additional master clock source within the transceiver bank.
• fPLL—In addition, dedicated fPLLs are available with precision frequency synthesis capabilities. fPLLs can be used to synthesize multiple clock frequencies from a single reference clock source and replace multiple reference oscillators for multi-protocol and multi-rate applications.

On the receiver side, each PMA has an independent channel PLL that allows analog tracking for clock-data recovery. Each PMA also has advanced equalization circuits that compensate for transmission losses across a wide frequency spectrum.

• Variable Gain Amplifier (VGA)—to optimize the receiver's dynamic range
• Continuous Time Linear Equalizer (CTLE)—to compensate for channel losses with lowest power dissipation
• Decision Feedback Equalizer (DFE)—to provide additional equalization capability on backplanes even in the presence of crosstalk and reflections
• On-Die Instrumentation (ODI)—to provide on-chip eye monitoring capabilities (Eye Viewer). This capability helps to optimize link equalization parameters during board bring-up and supports in-system link diagnostics and equalization margin testing

All link equalization parameters feature automatic adaptation using the new Advanced Digital Adaptive Parametric Tuning (ADAPT) circuit. This circuit is used to dynamically set DFE tap weights, adjust CTLE parameters, and optimize VGA gain and threshold voltage. Finally, optimal and consistent signal integrity is ensured by using the new hardened Precision Signal Integrity Calibration Engine (PreSICE) to automatically calibrate all transceiver circuit blocks on power-up. This gives the most link margin and ensures robust, reliable, and error-free operation.

Intel^® Stratix^® 10 PMA channels interface with core logic through configurable and bypassable PCS interface layers.

The PCS contains multiple gearbox implementations to decouple the PMA and PCS interface widths. This feature provides the flexibility to implement a wide range of applications with 8, 10, 16, 20, 32, 40, or 64 bit interface width between each transceiver and the core logic.

The PCS also contains hard IP to support a variety of standard and proprietary protocols across a wide range of data rates and encoding schemes. The Standard PCS mode provides support for 8B/10B encoded applications up to 12.5 Gbps. The Enhanced PCS mode supports 64B/66B and 64B/67B encoded applications up to 17.4 Gbps. The enhanced PCS mode also includes an integrated 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC) circuit. For highly customized implementations, a PCS Direct mode provides an interface up to 64 bits wide to allow for custom encoding and support for data rates up to 28.3 Gbps.

For more information about the PCS-Core interface or the double rate transfer mode, refer to the Intel^® Stratix^® 10 L- and H-Tile Transceiver PHY User Guide, and the Intel^® Stratix^® 10 E-Tile Transceiver PHY User Guide.

Intel^® Stratix^® 10 devices contain embedded PCI Express hard IP designed for performance, ease-of-use, increased functionality, and designer productivity.

The PCI Express hard IP consists of the PHY, Data Link, and Transaction layers. It also supports PCI Express Gen1/Gen2/Gen3 end point and root port, in x1/x2/x4/x8/x16 lane configurations. The PCI Express hard IP is capable of operating independently from the core logic (autonomous mode). This feature allows the PCI Express link to power up and complete link training in less than 100 ms, while the rest of the device is still in the process of being configured. The hard IP also provides added functionality, which makes it easier to support emerging features such as Single Root I/O Virtualization (SR-IOV) and optional protocol extensions.

The PCI Express hard IP has improved end-to-end data path protection using Error Checking and Correction (ECC). In addition, the hard IP supports configuration of the device via protocol (CvP) across the PCI Express bus at Gen1/Gen2/Gen3 rates.

Intel^® Stratix^® 10 devices have integrated Interlaken PCS hard IP supporting rates up to 17.4 Gbps per lane.

The Interlaken PCS hard IP is based on the proven functionality of the PCS developed for Intel’s previous generation FPGAs, which has demonstrated interoperability with Interlaken ASSP vendors and third-party IP suppliers. The Interlaken PCS hard IP is present in every transceiver channel in Intel^® Stratix^® 10 devices.

Intel^® Stratix^® 10 devices include IEEE 802.3 10-Gbps Ethernet (10GbE) compliant 10GBASE-R PCS and PMA hard IP. The scalable 10GbE hard IP supports multiple independent 10GbE ports while using a single PLL for all the 10GBASE-R PCS instantiations, which saves on core logic resources and clock networks.

The integrated serial transceivers simplify multi-port 10GbE systems compared to 10 GbE Attachment Unit Interface (XAUI) interfaces that require an external XAUI-to-10G PHY. Furthermore, the integrated transceivers incorporate signal conditioning circuits, which enable direct connection to standard 10G XFP and SFP+ pluggable optical modules. The transceivers also support backplane Ethernet applications and include a hard 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC) circuit that can be used for both 10G and 40G applications. The integrated 10G Ethernet hard IP and 10G transceivers save external PHY cost, board space and system power. The 10G Ethernet PCS hard IP and 10GBASE-KR FEC are present in every transceiver channel.

Intel^® Stratix^® 10 devices offer substantial external memory bandwidth, with up to ten 72 bit wide DDR4 memory interfaces running at up to 2666 Mbps.

This bandwidth is provided along with the ease of design, lower power, and resource efficiencies of hardened high-performance memory controllers. The external memory interfaces can be configured up to a maximum width of 144 bits when using either hard or soft memory controllers.

Each I/O bank contains 48 general purpose I/Os and a high-efficiency hard memory controller capable of supporting many different memory types, each with different performance capabilities. The hard memory controller is also capable of being bypassed and replaced by a soft controller implemented in the user logic. The I/Os each have a hardened double data rate (DDR) read/write path (PHY) capable of performing key memory interface functionality such as:

• Read/write leveling
• FIFO buffering to lower latency and improve margin
• Timing calibration
• On-chip termination

The timing calibration is aided by the inclusion of hard microcontrollers based on Intel’s Nios^® II technology, specifically tailored to control the calibration of multiple memory interfaces. This calibration allows the Intel^® Stratix^® 10 device to compensate for any changes in process, voltage, or temperature either within the Intel^® Stratix^® 10 device itself, or within the external memory device. The advanced calibration algorithms ensure maximum bandwidth and robust timing margin across all operating conditions.

In addition to parallel memory interfaces, Intel^® Stratix^® 10 devices support serial memory technologies such as the Hybrid Memory Cube (HMC). The HMC is supported by the Intel^® Stratix^® 10 high-speed serial transceivers, which connect up to four HMC links, with each link running at data rates of 15 Gbps (HMC short reach specification).

Intel^® Stratix^® 10 devices also feature general purpose I/Os capable of supporting a wide range of single-ended and differential I/O interfaces. LVDS rates up to 1.6 Gbps are supported, with each pair of pins having both a differential driver and a differential input buffer. This enables configurable direction for each LVDS pair.

Intel^® Stratix^® 10 devices use a similar adaptive logic module (ALM) as the previous generation Intel^® Arria^® 10 and Stratix^® V FPGAs, allowing for efficient implementation of logic functions and easy conversion of IP between the devices.

The ALM block diagram shown in the following figure has eight inputs with a fracturable look-up table (LUT), two dedicated embedded adders, and four dedicated registers.

Key features and capabilities of the ALM include:

• High register count with 4 registers per 8-input fracturable LUT, operating in conjunction with the new Intel^® Hyperflex™ architecture, enables Intel^® Stratix^® 10 devices to maximize core performance at very high core logic utilization
• Implements select 7-input logic functions, all 6-input logic functions, and two independent functions consisting of smaller LUT sizes (such as two independent 4-input LUTs) to optimize core logic utilization

The Intel^® Quartus^® Prime software takes advantage of the ALM logic structure to deliver the highest performance, optimal logic utilization, and lowest compile times. The Intel^® Quartus^® Prime software simplifies design reuse as it automatically maps legacy designs into the Intel^® Stratix^® 10 ALM architecture.

Core clocking in Intel^® Stratix^® 10 devices makes use of programmable clock tree synthesis.

This technique uses dedicated clock tree routing and switching circuits, and allows the Intel^® Quartus^® Prime software to create the exact clock trees required for your design. Clock tree synthesis minimizes clock tree insertion delay, reduces dynamic power dissipation in the clock tree and allows greater clocking flexibility in the core while still maintaining backwards compatibility with legacy global and regional clocking schemes.

The core clock network in Intel^® Stratix^® 10 devices supports the new Intel^® Hyperflex™ core architecture at clock rates up to 1 GHz. It also supports the hard memory controllers up to 2666 Mbps with a quarter rate transfer to the core. The core clock network is supported by dedicated clock input pins, fractional clock synthesis PLLs, and integer I/O PLLs.

Intel^® Stratix^® 10 devices have up to 32 fractional synthesis PLLs (fPLL) available for use with transceivers or in the core fabric.

The fPLLs are located in the 3D SiP transceiver L-tiles and H-tiles, eight per tile, adjacent to the transceiver channels. The fPLLs can be used to reduce both the number of oscillators required on the board and the number of clock pins required, by synthesizing multiple clock frequencies from a single reference clock source. In addition to synthesizing reference clock frequencies for the transceiver transmit PLLs, the fPLLs can also be used directly for transmit clocking. Each fPLL can be independently configured for conventional integer mode, or enhanced fractional synthesis mode with third-order delta-sigma modulation.

In addition to the fPLLs, Intel^® Stratix^® 10 devices contain up to 24 integer I/O PLLs (IOPLLs) available for general purpose use in the core fabric and for simplifying the design of external memory interfaces and high-speed LVDS interfaces. The IOPLLs are located in each bank of 48 general purpose I/O, 1 per I/O bank, adjacent to the hard memory controllers and LVDS SerDes in each I/O bank. This makes it easier to close timing because the IOPLLs are tightly coupled with the I/Os that need to use them. The IOPLLs can be used for general purpose applications in the core such as clock network delay compensation and zero-delay clock buffering.

Intel^® Stratix^® 10 devices contain two types of embedded memory blocks: M20K (20 Kb) and MLAB (640 bit).

The M20K and MLAB blocks are familiar block sizes carried over from previous Intel device families. The MLAB blocks are ideal for wide and shallow memories, while the M20K blocks are intended to support larger memory configurations and include hard ECC. Both M20K and MLAB embedded memory blocks can be configured as a single-port or dual-port RAM, FIFO, ROM, or shift register. These memory blocks are highly flexible and support a number of memory configurations as shown in Table 10.

The Intel^® Stratix^® 10 DSP blocks are based upon the Variable Precision DSP Architecture used in Intel’s previous generation devices. They feature hard fixed point and IEEE 754 compliant floating point capability.

The DSP blocks can be configured to support signal processing with precision ranging from 18x19 up to 54x54. A pipeline register has been added to increase the maximum operating frequency of the DSP block and reduce power consumption.

Each DSP block can be independently configured at compile time as either dual 18x19 or a single 27x27 multiply accumulate. With a dedicated 64 bit cascade bus, multiple variable precision DSP blocks can be cascaded to implement even higher precision DSP functions efficiently.

In floating point mode, each DSP block provides one single precision floating point multiplier and adder. Floating point additions, multiplications, mult-adds and mult-accumulates are supported.

The following table shows how different precisions are accommodated within a DSP block, or by utilizing multiple blocks.

Complex multiplication is very common in DSP algorithms. One of the most popular applications of complex multipliers is the FFT algorithm. This algorithm has the characteristic of increasing precision requirements on only one side of the multiplier. The Variable Precision DSP block supports the FFT algorithm with proportional increase in DSP resources as the precision grows.

For FFT applications with high dynamic range requirements, the Intel FFT IP Core offers an option of single precision floating point implementation with resource usage and performance similar to high precision fixed point implementations.

Other features of the DSP block include:

• Hard 18 bit and 25 bit pre-adders
• Hard floating point multipliers and adders
• 64 bit dual accumulator (for separate I, Q product accumulations)
• Cascaded output adder chains for 18 and 27 bit FIR filters
• Embedded coefficient registers for 18 and 27 bit coefficients
• Fully independent multiplier outputs
• Inferability using HDL templates supplied by the Intel^® Quartus^® Prime software for most modes

The Variable Precision DSP block is ideal to support the growing trend towards higher bit precision in high performance DSP applications. At the same time, it can efficiently support the many existing 18 bit DSP applications, such as high definition video processing and remote radio heads. With the Variable Precision DSP block architecture and hard floating point multipliers and adders, Intel^® Stratix^® 10 devices can efficiently support many different precision levels up to and including floating point implementations. This flexibility can result in increased system performance, reduced power consumption, and reduce architecture constraints on system algorithm designers.

The Intel^® Stratix^® 10 SoC Hard Processor System (HPS) is Intel’s third generation HPS. Leveraging the performance of Intel 14 nm tri-gate technology, Intel^® Stratix^® 10 SoC devices more than double the performance of previous generation SoCs with an integrated quad-core 64-bit Arm* Cortex* -A53. The HPS also enables system-wide hardware virtualization capabilities by adding a system memory management unit. These architecture improvements ensure that Intel^® Stratix^® 10 SoCs meet the requirements of current and future embedded markets, including wireless and wireline communications, data center acceleration, and numerous military applications.

Intel^® Stratix^® 10 devices leverage the advanced Intel 14 nm tri-gate process technology, the all new Intel^® Hyperflex™ core architecture to enable Hyper-Folding, power gating, and several optional power reduction techniques to reduce total power consumption by as much as 70% compared to previous generation high-performance Stratix^® V devices.

Intel^® Stratix^® 10 standard power devices (-V) are SmartVID devices. The core voltage supplies (VCC and VCCP) for each SmartVID device must be driven by a PMBus voltage regulator dedicated to that Intel^® Stratix^® 10 device. Use of a PMBus voltage regulator for each SmartVID (-V) device is mandatory; it is not an option. A code is programmed into each SmartVID device during manufacturing that allows the PMBus voltage regulator to operate at the optimum core voltage to meet the device performance specifications.

With the new Intel^® Hyperflex™ core architecture, designs can run 2X faster than previous generation FPGAs. With 2X performance and same required throughput, architects can cut the data path width in half to save power. This optimization is called Hyper-Folding. Additionally, power gating reduces static power of unused resources in the FPGA by powering them down. The Intel^® Quartus^® Prime software automatically powers down specific unused resource blocks such as DSP and M20K blocks, at configuration time.

The optional power reduction techniques in Intel^® Stratix^® 10 devices include:

• Available Low Static Power Devices— Intel^® Stratix^® 10 devices are available with a fixed core voltage that provides lower static power than the SmartVID standard power devices, while maintaining device performance

Furthermore, Intel^® Stratix^® 10 devices feature Intel’s low power transceivers and include a number of hard IP blocks that not only reduce logic resources but also deliver substantial power savings compared to soft implementations. In general, hard IP blocks consume up to 50% less power than the equivalent soft logic implementations.

Configuration via protocol using PCI Express* allows the FPGA to be configured across the PCI Express* bus, simplifying the board layout and increasing system integration. Making use of the embedded PCI Express* hard IP operating in autonomous mode before the FPGA is configured, this technique allows the PCI Express* bus to be powered up and active within the 100 ms time allowed by the PCI Express* specification. Intel^® Stratix^® 10 devices also support partial reconfiguration across the PCI Express* bus which reduces system down time by keeping the PCI Express* link active while the device is being reconfigured.

In addition to lowering power and cost, partial reconfiguration also increases the effective logic density by removing the necessity to place in the FPGA those functions that do not operate simultaneously. Instead, these functions can be stored in external memory and loaded as needed. This reduces the size of the required FPGA by allowing multiple applications on a single FPGA, saving board space and reducing power. The partial reconfiguration process is built on top of the proven incremental compile design flow in the Intel^® Quartus^® Prime design software

Dynamic reconfiguration in Intel^® Stratix^® 10 devices allows transceiver data rates, protocols and analog settings to be changed dynamically on a channel-by-channel basis while maintaining data transfer on adjacent transceiver channels. Dynamic reconfiguration is ideal for applications that require on-the-fly multiprotocol or multi-rate support. Both the PMA and PCS blocks within the transceiver can be reconfigured using this technique. Dynamic reconfiguration of the transceivers can be used in conjunction with partial reconfiguration of the FPGA to enable partial reconfiguration of both core and transceivers simultaneously.

Intel^® Stratix^® 10 FPGAs and SoCs offer robust SEU error detection and correction circuitry. The detection and correction circuitry includes protection for Configuration RAM (CRAM) programming bits and user memories. The CRAM is protected by a continuously running parity checker circuit with integrated ECC that automatically corrects one or two bit errors and detects higher order multibit errors.

The physical layout of the CRAM array is optimized to make the majority of multi-bit upsets appear as independent single-bit or double-bit errors which are automatically corrected by the integrated CRAM ECC circuitry. In addition to the CRAM protection, the user memories also include integrated ECC circuitry and are layout optimized for error detection and correction.

The SEU error detection and correction hardware is supported by both soft IP and the Intel^® Quartus^® Prime software to provide a complete SEU mitigation solution. The components of the complete solution include:

• Hard error detection and correction for CRAM and user M20K memory blocks
• Optimized physical layout of memory cells to minimize probability of SEU
• Sensitivity processing soft IP that reports if CRAM upset affects a used or unused bit
• Fault injection soft IP with the Intel^® Quartus^® Prime software support that changes state of CRAM bits for testing purposes
• Hierarchy tagging in the Intel^® Quartus^® Prime software
• Triple Mode Redundancy (TMR) used for the Secure Device Manager and critical on-chip state machines

In addition to the SEU mitigation features listed above, the Intel 14 nm tri-gate process technology used for Intel^® Stratix^® 10 devices is based on FinFET transistors which have reduced SEU susceptibility versus conventional planar transistors.