In addition to the coherent and non-coherent protocol interfaces that are required for high-performance acceleration applications, Intel^® Stratix^® 10 DX FPGAs deliver improved core logic performance compared to previous generation high-performance FPGAs, with densities up to 2.8 million LEs in a monolithic fabric.

The devices also feature up to 84 full-duplex transceivers on separate transceiver tiles, a subset of which are capable of supporting data rates up to 57.8 Gbps PAM4 and 28.9 Gbps NRZ for both short reach and backplane driving applications. External memory interfaces up to 2666 Mbps DDR4 are achieved using hard memory controllers, and some DX variant devices include in-package 3D stacked HBM2 DRAM memory capable of supporting 512 GByte/s memory bandwidth. Select devices contain an embedded hard processor system (HPS) based on an application-class quad-core 64-bit Arm* Cortex* -A53, running at clock rates up to 1.5 GHz, including processor peripherals and high-bandwidth buses to and from the FPGA logic fabric.

The high-performance monolithic FPGA fabric is based on the Intel^® Hyperflex™ core architecture that includes additional Hyper-Registers everywhere throughout the interconnect routing and at the inputs of all functional blocks. The core fabric also contains an enhanced logic array utilizing Intel’s adaptive logic module (ALM) and a rich set of high-performance building blocks including:

• M20K, 20 Kb embedded SRAM memory blocks
• eSRAM, 47.25 Mb embedded SRAM memory blocks (in select devices)
• Variable precision DSP blocks with hard fixed point and IEEE 754 compliant hard floating-point
• General purpose IO cells with integer PLLs in every IO bank
• Hard memory controllers and PHY for external memory interfaces
• Hard memory controllers for in-package 3D stacked HBM2 DRAM memory (in select devices)

To clock these fabric building blocks, Intel^® Stratix^® 10 DX FPGAs use programmable clock tree synthesis, which uses dedicated clock tree routing to synthesize only those branches of the clock trees required for the application.

The high-speed serial transceivers contain both the physical medium attachment (PMA) and the physical coding sublayer (PCS) required to implement a variety of industry standard protocols. In addition to the hard PCS for each transceiver, Intel^® Stratix^® 10 DX devices contain hard PCI Express* IP that supports up to Gen4 x16 lane configuration, hard Intel^® UPI IP in select devices that supports Home Agent soft IP, and hard 10/25/100 Gbps Ethernet MAC IP with dedicated Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514). These hardened intellectual property blocks free up valuable core logic resources, save power, and increase your productivity.

All Intel^® Stratix^® 10 DX devices support in-system, fine-grained partial reconfiguration of the logic array, allowing logic add and subtract from the system while it is operating.

Intel^® Stratix^® 10 DX devices contain one or more P-tiles, each P-tile containing up to 20 full-duplex transceiver channels, along with PCIe* Gen4 x16 hard IP and Intel^® UPI hard IP. If all 20 channels from the P-tile are available in the device, the P-tile can be configured to support either a PCIe* interface or an Intel^® UPI interface. If only 16 channels are available, the P-tile supports PCIe* but does not support Intel^® UPI which requires all 20 channels. Support for protocols other than PCIe* or Intel^® UPI is not possible with the P-tile; it is not possible to bypass the hard IP blocks and connect the P-tile transceivers directly to the FPGA fabric.

Each E-tile contains up to 24 full-duplex dual-mode transceivers, each transceiver capable of supporting both Pulse Amplitude Modulation with 4 levels (PAM4) up to 57.8 Gbps, and non-return-to-zero (NRZ) up to 28.9 Gbps. In addition to the transceivers, each E-tile contains multiple instances of 10/25/100 Gbps Ethernet MAC + FEC hard IP blocks. Both Reed-Solomon and KP FEC hard IP blocks are included, allowing complete Ethernet interfaces to be implemented, simplifying the design of complex multi-port Ethernet systems.

For more information about the E-tile transceivers and the E-tile Ethernet hard IP, refer to the Intel^® Stratix^® 10 E-Tile Transceiver PHY User Guide.

In addition to the bandwidth delivered by the in-package HBM2 DRAM near memory (in selected devices), all Intel^® Stratix^® 10 DX devices offer substantial external memory bandwidth, supporting DDR4 memory interfaces running at up to 2666 Mbps and DDR-T memory interfaces at up to 2400 megatransfers per second.

This bandwidth is provided along with the ease of design, lower power, and resource efficiencies of hardened high-performance memory controllers. The external memory interfaces can be configured up to a maximum width of 144 bits when using either hard or soft memory controllers.

Each I/O bank contains 48 general purpose I/Os and a high-efficiency hard memory controller capable of supporting many different memory types, each with different performance capabilities. The hard memory controller is also capable of being bypassed and replaced by a soft controller implemented in user logic. The I/Os each have a hardened double data rate (DDR) read/write path (PHY) capable of performing key memory interface functionality such as:

• Read/write leveling
• FIFO buffering to lower latency and improve margin
• Timing calibration
• On-chip termination

The timing calibration is aided by the inclusion of hard microcontrollers based on Intel’s Nios^® II technology, specifically tailored to control the calibration of multiple memory interfaces. This calibration allows the Intel^® Stratix^® 10 DX device to compensate for any changes in process, voltage, or temperature either within the device itself, or within the external memory device. The advanced calibration algorithms ensure maximum bandwidth and robust timing margin across all operating conditions. For the list of features available with the Intel^® DDR-T memory controller IP, see External Memory Interface and the DDR-T Memory Controller IP User Guide. For access to the DDR-T Memory Controller IP User Guide, contact My Intel support.

Intel^® Stratix^® 10 DX devices also feature general purpose I/Os capable of supporting a wide range of single-ended and differential I/O interfaces. LVDS rates up to 1.6 Gbps are supported, with each pair of pins having both a differential driver and a differential input buffer. This enables configurable direction for each LVDS pair.

Intel^® Stratix^® 10 DX devices use a similar adaptive logic module (ALM) as the previous generation Intel^® Arria^® 10 and Stratix^® V FPGAs, allowing for efficient implementation of logic functions and easy conversion of IP between the devices.

The ALM block diagram shown in the following figure has eight inputs with a fracturable look-up table (LUT), two dedicated embedded adders, and four dedicated registers.

Key features and capabilities of the ALM include:

• High register count with 4 registers per 8-input fracturable LUT, operating in conjunction with the new Intel^® Hyperflex™ architecture, enables Intel^® Stratix^® 10 DX devices to maximize core performance at very high core logic utilization
• Implements select 7-input logic functions, all 6-input logic functions, and two independent functions consisting of smaller LUT sizes (such as two independent 4-input LUTs) to optimize core logic utilization

The Intel^® Quartus^® Prime software takes advantage of the ALM logic structure to deliver the highest performance, optimal logic utilization, and lowest compile times. The Intel^® Quartus^® Prime software simplifies design reuse as it automatically maps legacy designs into the Intel^® Stratix^® 10 ALM architecture.

Core clocking in Intel^® Stratix^® 10 DX devices makes use of programmable clock tree synthesis.

This technique uses dedicated clock tree routing and switching circuits, and allows the Intel^® Quartus^® Prime software to create the exact clock trees required for your design. Clock tree synthesis minimizes clock tree insertion delay, reduces dynamic power dissipation in the clock tree and allows greater clocking flexibility in the core while still maintaining backwards compatibility with legacy global and regional clocking schemes.

The core clock network in Intel^® Stratix^® 10 DX devices supports the high-performance Intel^® Hyperflex™ core architecture and also supports the hard memory controllers at rates up to 2666 Mbps with a quarter rate transfer to the core. The core clock network is driven by either dedicated clock input pins, or integer I/O PLLs.

Intel^® Stratix^® 10 DX devices contain up to 24 integer I/O PLLs (IOPLLs) available for general purpose use in the core fabric and for simplifying the design of external memory interfaces and high-speed LVDS interfaces. The IOPLLs are located in each bank of 48 general purpose I/O, one per I/O bank, adjacent to the hard memory controllers and LVDS SerDes in each I/O bank. This makes it easier to close timing because the IOPLLs are tightly coupled with I/Os that need to use them. The IOPLLs can be used for general purpose applications in the core such as clock network delay compensation and zero-delay clock buffering

Intel^® Stratix^® 10 DX devices contain three types of embedded memory blocks: eSRAM (47.25 Mbit), M20K (20 Kb), and MLAB (640 bit). This variety of on-chip memory provides fast access times and low latency for applications such as wide and deep FIFOs and variable buffers. Combined with the in-package memory provided by the HBM2 DRAM stacks in select devices, the internal embedded memory completes the memory hierarchy in Intel^® Stratix^® 10 DX devices.

The eSRAM blocks are a new innovation in Intel^® Stratix^® 10 devices. These large embedded SRAM blocks are tightly coupled to the core fabric and are directly accessible with no need for a separate memory controller. Each eSRAM block is arranged as 8 channels, 42 banks per channel, with a total capacity of 47.25 Mbits running at clock rates up to 750 MHz. Within the eSRAM block, each channel has a bus width of 72 bit read and 72 bit write, and has one READ and one WRITE per channel. This allows each eSRAM block to support a total aggregate bandwidth (read + write) of up to 864 Gbps.

The eSRAM block is implemented as a simple dual port memory with concurrent read and write access per channel, and includes integrated hard ECC generation and checking. Compared to an off-chip SRAM solution, the eSRAM block allows you to reduce system power and save board space and cost.

The M20K and MLAB blocks are familiar block sizes carried over from previous Intel device families. The MLAB blocks are ideal for wide and shallow memories, while the M20K blocks are intended to support larger memory configurations and include hard ECC. Both M20K and MLAB embedded memory blocks can be configured as a single-port or dual-port RAM, FIFO, ROM, or shift register. These memory blocks are highly flexible and support a number of memory configurations as shown in the table.

The Intel^® Stratix^® 10 DX DSP blocks are based upon the Variable Precision DSP Architecture used in Intel’s previous generation devices. They feature hard fixed point and IEEE 754 compliant floating point capability.

The DSP blocks can be configured to support signal processing with precision ranging from 18x19 up to 54x54. A pipeline register has been added to increase the maximum operating frequency of the DSP block and reduce power consumption.

Each DSP block can be independently configured at compile time as either dual 18x19 or a single 27x27 multiply accumulate. With a dedicated 64 bit cascade bus, multiple variable precision DSP blocks can be cascaded to implement even higher precision DSP functions efficiently.

In floating point mode, each DSP block provides one single precision floating point multiplier and adder. Floating point additions, multiplications, mult-adds and mult-accumulates are supported.

The following table shows how different precisions are accommodated within a DSP block, or by utilizing multiple blocks.

Complex multiplication is very common in DSP algorithms. One of the most popular applications of complex multipliers is the FFT algorithm. This algorithm has the characteristic of increasing precision requirements on only one side of the multiplier. The Variable Precision DSP block supports the FFT algorithm with proportional increase in DSP resources as the precision grows.

For FFT applications with high dynamic range requirements, the Intel FFT IP Core offers an option of single precision floating point implementation with resource usage and performance similar to high precision fixed point implementations.

Other features of the DSP block include:

• Hard 18 bit and 25 bit pre-adders
• Hard floating point multipliers and adders
• 64 bit dual accumulator (for separate I, Q product accumulations)
• Cascaded output adder chains for 18 and 27 bit FIR filters
• Embedded coefficient registers for 18 and 27 bit coefficients
• Fully independent multiplier outputs
• Inferability using HDL templates supplied by the Intel^® Quartus^® Prime software for most modes

The Variable Precision DSP block is ideal to support the growing trend towards higher bit precision in high performance DSP applications. At the same time, it can efficiently support the many existing 18 bit DSP applications, such as high definition video processing and remote radio heads. With the Variable Precision DSP block architecture and hard floating point multipliers and adders, Intel^® Stratix^® 10 DX devices can efficiently support many different precision levels up to and including floating point implementations. This flexibility can result in increased system performance, reduced power consumption, and reduce architecture constraints on system algorithm designers.

The Hard Processor System (HPS) in select Intel^® Stratix^® 10 DX devices is Intel's third generation HPS. Leveraging the performance of Intel 14 nm tri-gate technology, the HPS provides more than double the performance of previous generation devices with an integrated quad-core 64-bit Arm* Cortex* -A53. The HPS also enables system-wide hardware virtualization capabilities by adding a system memory management unit.

Intel^® Stratix^® 10 DX devices use the advanced Intel 14 nm tri-gate process technology, the all new Intel^® Hyperflex™ core architecture to enable Hyper-Folding, power gating, and optional power reduction techniques to reduce total power consumption by as much as 70% compared to previous generation high-performance Stratix^® V devices.

Intel^® Stratix^® 10 standard power devices (-V) are SmartVID devices. The core voltage supplies (VCC and VCCP) for each SmartVID device must be driven by a PMBus voltage regulator dedicated to that Intel^® Stratix^® 10 device. Use of a PMBus voltage regulator for each SmartVID (-V) device is mandatory; it is not an option. A code is programmed into each SmartVID device during manufacturing that allows the PMBus voltage regulator to operate at the optimum core voltage to meet the device performance specifications.

With the new Intel^® Hyperflex™ core architecture, designs can run faster than previous generation FPGAs. With faster performance and same required throughput, architects can reduce the width of the data path to save power. This optimization is called Hyper-Folding. Additionally, power gating reduces static power of unused resources in the FPGA by powering them down. The Intel^® Quartus^® Prime software automatically powers down specific unused resource blocks such as DSP and M20K blocks, at configuration time.

Furthermore, Intel^® Stratix^® 10 DX devices feature Intel’s low power transceivers and include a number of hard IP blocks that not only reduce logic resources but also deliver substantial power savings compared to soft implementations. In general, hard IP blocks consume up to 50% less power than the equivalent soft logic implementations.

Configuration via protocol using PCI Express* allows the FPGA to be configured across the PCI Express* bus, simplifying the board layout and increasing system integration. Making use of the embedded PCI Express* hard IP operating in autonomous mode before the FPGA is configured, this technique allows the PCI Express* bus to be powered up and active within the 100 ms time allowed by the PCI Express* specification. Intel^® Stratix^® 10 DX devices also support partial reconfiguration across the PCI Express* bus which reduces system down time by keeping the PCI Express* link active while the device is being reconfigured.

In addition to lowering power and cost, partial reconfiguration also increases the effective logic density by removing the necessity to place in the FPGA those functions that do not operate simultaneously. Instead, these functions can be stored in external memory and loaded as needed. This reduces the size of the required FPGA by allowing multiple applications on a single FPGA, saving board space and reducing power. The partial reconfiguration process is built on top of the proven incremental compile design flow in the Intel^® Quartus^® Prime design software

Dynamic reconfiguration in Intel^® Stratix^® 10 DX devices allows transceiver data rates, protocols and analog settings to be changed dynamically on a channel-by-channel basis while maintaining data transfer on adjacent transceiver channels. Dynamic reconfiguration is ideal for applications that require on-the-fly multiprotocol or multi-rate support. Both the PMA and PCS blocks within the transceiver can be reconfigured using this technique. Dynamic reconfiguration of the transceivers can be used in conjunction with partial reconfiguration of the FPGA to enable partial reconfiguration of both core and transceivers simultaneously.

Intel^® Stratix^® 10 DX devices offer robust SEU error detection and correction circuitry. The detection and correction circuitry includes protection for Configuration RAM (CRAM) programming bits and user memories. The CRAM is protected by a continuously running parity checker circuit with integrated ECC that automatically corrects one or two bit errors and detects higher order multibit errors.

The physical layout of the CRAM array is optimized to make the majority of multi-bit upsets appear as independent single-bit or double-bit errors which are automatically corrected by the integrated CRAM ECC circuitry. In addition to the CRAM protection, user memories also include integrated ECC circuitry and are layout optimized for error detection and correction.

The SEU error detection and correction hardware is supported by both soft IP and the Intel^® Quartus^® Prime software to provide a complete SEU mitigation solution. The components of the complete solution include:

• Hard error detection and correction for CRAM and user eSRAM and M20K memory blocks
• Optimized physical layout of memory cells to minimize probability of SEU
• Sensitivity processing soft IP that reports if CRAM upset affects a used or unused bit
• Fault injection soft IP with the Intel^® Quartus^® Prime software support that changes state of CRAM bits for testing purposes
• Hierarchy tagging in the Intel^® Quartus^® Prime software
• Triple Mode Redundancy (TMR) used for the Secure Device Manager and critical on-chip state machines

In addition to the SEU mitigation features listed above, the Intel 14 nm tri-gate process technology used for Intel^® Stratix^® 10 DX devices is based on FinFET transistors which have reduced SEU susceptibility versus conventional planar transistors.