PDF Documentation
- Stratix II Device Handbook (Complete Two-Volume Set) (5 MB)
- Stratix II Device Handbook, Volume 1 (ver 4.5, Apr 2011, 3 MB)
- Stratix II Device Handbook, Volume 2 (ver 4.5, Apr 2009, 3 MB)
- Chapter 1. Introduction (ver 4.2, Jul 2007, 132 KB)
- Chapter 2. Stratix II Architecture (ver 4.3, May 2007, 1,011 KB)
- Chapter 3. Configuration & Testing (ver 4.2, May 2007, 165 KB)
- Chapter 4. Hot Socketing & Power-On Reset (ver 3.2, Apr 2006, 102 KB)
- Chapter 5. DC & Switching Characteristics (ver 4.5, Apr 2011, 2 MB)
- Chapter 6. Reference & Ordering Information (ver 2.2, Apr 2011, 150 KB)
Section I. Clock Management
- Chapter 1. PLLs in Stratix II and Stratix II GX Devices (ver 4.6, Jul 2009, 634 KB)
Section II. Memory
- Chapter 2. TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices (ver 4.5, Jan 2008, 376 KB)
- Chapter 3. External Memory Interfaces in Stratix II and Stratix II GX Devices (ver 4.5, Jan 2008, 387 KB)
Section III. I/O Standards
- Chapter 4. Selectable I/O Standards in Stratix II and Stratix II GX Devices (ver 4.6, Jan 2008, 491 KB)
- Chapter 5. High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices (ver 2.2, Jan 2008, 337 KB)
Section IV. Digital Signal Processing (DSP)
- Chapter 6. DSP Blocks in Stratix II and Stratix II GX Devices (ver 2.2, Jan 2008, 339 KB)
Section V. Configuration and Remote System Upgrades
- Chapter 7. Configuring Stratix II and Stratix II GX Devices (ver 4.5, Jan 2008, 993 KB)
- Chapter 8. Remote System Upgrades with Stratix II and Stratix II GX Devices (ver 4.5, Jan 2008, 291 KB)
- Chapter 9. IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix II and Stratix II GX Devices (ver 3.3, Jan 2008, 272 KB)
Section VI. PCB Layout Guidelines
- Chapter 10. Package Information for Stratix II & Stratix II GX Devices (ver 4.3, May 2007, 477 KB)
- Chapter 11. High-Speed Board Layout Guidelines (ver 1.4, May 2007, 654 KB)
User Guides
- SCFIFO and DCFIFO Megafunctions User Guide (ver 8.2, May 2013, 496 KB)
- Double Data Rate I/O Megafunction User Guide (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) (ver 6.1, Jan 2013, 694 KB)
- External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide (ver 7.3, Jan 2010, 3 MB)
- DDR Timing Wizard User Guide (ver 3.0, Nov 2007, 2 MB)
- PowerPlay Early Power Estimator User Guide for Stratix II, Stratix II GX, and HardCopy II (ver 1.2, Jan 2007, 3 MB)
Manuals
- Advanced Synthesis Cookbook (ver 6.0, Jul 2011, 3 MB)
- Nios Development Board Stratix II Edition Reference Manual (ver 1.3, May 2007, 1 MB)
- Stratix II EP2S180 DSP Development Board Reference Manual (ver 1.0, Aug 2005, 549 KB)
- AN 717: Nios II Gen2 Hardware Development Tutorial (ver 2014.09.22, Sep 2014, 613 KB)
- AN 358: Thermal Management for FPGAs (ver 4.0, Mar 2012, 547 KB)
- AN 432: Using Different PLL Settings Between Stratix II and HardCopy II Devices (ver 1.2, Mar 2010, 149 KB)
- AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices (ver 6.0, Oct 2009, 3 MB)
- AN 326: Interfacing QDRII+ & QDRII with Stratix II, Stratix II GX, Stratix, & Stratix GX Devices (ver 5.1, May 2008, 2 MB)
- AN 425: Using the Command-Line Jam STAPL Solution for Device Programming (ver 2014.09.22, Sep 2014, 1 MB)
- AN 114: Designing with High-Density BGA Packages for Altera Devices (ver 5.3, Sep 2014, 844 KB)
- AN 367: Implementing PLL Reconfiguration in Stratix II Devices (ver 2.2, Jul 2012, 628 KB)
- AN 477: Designing RGMII Interface with FPGA and HardCopy Devices (ver 2.0, Jan 2010, 519 KB)
- AN 341: Using the Design Security Feature in Stratix II and Stratix II GX Devices (ver 2.3, Sep 2009, 1 MB)
- AN 462: Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction (ver 1.3, Apr 2009, 784 KB)
- AN 327: Interfacing DDR SDRAM with Stratix II Devices (ver 3.2, Sep 2008, 938 KB)
- AN 357: Error Detection & Recovery Using CRC in Altera FPGA Devices (ver 1.4, Jul 2008, 371 KB)
- AN 449: External Memory Interface Design Guidelines for Stratix II, Stratix II GX, and Arria GX Devices (ver 1.2, Sep 2007, 284 KB)
- AN 366: Understanding I/O Output Timing for Altera Devices (ver 1.0, Jul 2006, 311 KB)
- AN 409: Design Example Using the altlvds Megafunction & the External PLL Option in Stratix II Devices (ver 1.0, Mar 2006, 244 KB)
- AN 411: Understanding PLL Timing for Stratix II Devices (ver 1.0, Mar 2006, 1 MB)
- AN 325: Interfacing RLDRAM II with Stratix II, Stratix & Stratix GX Devices (ver 3.1, Nov 2005, 2 MB)
- AN 384: Using Calibrated Series On-Chip Termination in Stratix II Devices (ver 1.0, Apr 2005, 116 KB)
- AN 379: Active Serial Memory Interface Controller Reference Design (ver 1.0, Mar 2005, 191 KB)
- AN 306: Implementing Multipliers in FPGA Devices (ver 3.0, Jul 2004, 733 KB)
- AN 355: Stratix II Device System Power Considerations (ver 1.0, Jun 2004, 274 KB)
- AN 315: Guidelines for Designing High-Speed FPGA PCBs (ver 1.1, Feb 2004, 2 MB)
- Versatile Digital QAM Modulator (ver 2.0, Dec 2010, 553 KB)
- Basic Principles of Signal Integrity (ver 1.3, Dec 2007, 548 KB)
- Implementation of the Smith-Waterman Algorithm on a Reconfigurable Supercomputing Platform (ver 1.0, Sep 2007, 1 MB)
- FPGA Performance Benchmarking Methodology (ver 1.6, Aug 2007, 246 KB)
- SEmulation: Turbocharging the FPGA Development Process (ver 1.0, Mar 2007, 1 MB)
- Stratix II Performance and Logic Efficiency Analysis (ver 2.0, Sep 2006, 1 MB)
- Stratix II vs. Virtex-4 Performance Comparison (ver 2.0, Sep 2006, 505 KB)
- Stratix II DDR2 System Validation Summary (ver 1.0, May 2006, 1 MB)
- Architectural Differences Between Stratix II & Stratix Devices (ver 1.1, Jan 2006, 324 KB)
- Stratix II vs. Virtex-4 Density Comparison (ver 2.2, Aug 2005, 264 KB)
- Input Signal Edge Rate Guidance (ver 1.0, Jun 2005, 63 KB)
- FPGAs for High-Performance DSP Applications (ver 1.1, May 2005, 119 KB)
- Using Parity to Detect Memory Errors in Stratix Devices (ver 1.2, Feb 2005, 97 KB)
- Stratix II DSP Performance (ver 2.0, Jan 2005, 241 KB)
- Stratix vs. Virtex-II Pro FPGA Performance Analysis (ver 1.1, Nov 2004, 146 KB)
- Benefits of Altera's High-Speed DDR2 SDRAM Memory Interface Solution (ver 1.0, May 2004, 273 KB)
- Implementing a Queue Manager in Traffic Management Systems (ver 1.1, Feb 2004, 125 KB)
- The Need for Dynamic Phase Alignment in High-Speed FPGAs (ver 1.1, Feb 2004, 71 KB)
- Altera Hot-Socketing & Power-Sequencing Advantages (ver 1.2, Feb 2004, 79 KB)
- MorphIO: An I/O Reconfiguration Solution for Altera Devices (ver 1.0, May 2003, 46 KB)
Errata Sheets
- Stratix II FPGA Family Errata Sheet (ver 2.1, Oct 2008, 224 KB)
Technical Briefs
- TB 086: Stratix II Military Temperature Range Support (ver 2.0, Oct 2007, 34 KB)
- TB 091: External Memory Interface Options for Stratix II Devices (ver 1.2, Mar 2007, 581 KB)
Product Overview
- Altera wireless solutions - 3GPP Long-Term Evolution (ver 1.0, Jan 2008, 68 KB)
- Accelerating applications on coprocessing platforms (ver 1.0, Jul 2007, 104 KB)
Device Pin-Out Files
- Pin-Outs (TXT) (Jun 2007, 39 KB)
- Pin-Outs (TXT) (Jun 2007, 44 KB)
- Pin-Outs (TXT) (Mar 2007, 79 KB)
- Pin-Outs (TXT) (Mar 2007, 41 KB)
- Pin-Outs (TXT) (Feb 2007, 117 KB)
- Pin-Outs (TXT) (Feb 2007, 115 KB)
- Pin-Outs (TXT) (ver 2.0, Feb 2007, 98 KB)
Process Change Notifications
- PCN 1205 Rev 1.3.0 Additional Assembly Source (ASE) and Transition to Center Pin Gate Mold for FBGA Packages (Jan 2013, 539 KB)
- PCN 0902 Rev 1.1.0 Additional Assembly Source and Bill of Material Change for Altera Flip Chip Products (Feb 2010, 620 KB)
Inserts and Advertorials
- Protecting IP Through FPGA Design Security (ver 1.0, Oct 2006, 933 KB)
(advertorial)
Application Briefs
- Understanding FLEX 8000 Timing (ver 1.0, Jun 2005, 96 KB)