Intel® FPGAs and Programmable Devices / SoCs / Portfolio / Cyclone V Soc / Cyclone® V SoC FPGAs Support

Cyclone® V SoC FPGAs Support

  • Cyclone® V I/O Timing Spreadsheet
  • Cyclone V SoC Device Design Guideleines 
  • Cyclone V FPGA Device Design Guidelines (PDF)
  • Cyclone V Errata (PDF)
  • Cyclone V SX, ST and SE SoC Device Errata
  • Known Cyclone V Issues
  • Cyclone V SoC HPS Address Map and Register Definition (HTML)
  • Cyclone V SoC HPS Address Map and Register Definitions (ZIP) 
  • Cyclone V SoC HPS Release Notes
  • All Packaging Specifications and Dimensions
  • Cyclone V Device Family Pin Connection Guidelines (PDF)
  • Cyclone V differential pad placement rule and pad mapping files
  • Device Pin-Outs
  • BSDL Files
  • Board Design Guidelines
  • Cyclone V SoC HPS Supported Flash Devices

QUICK LINKS

  • Cyclone V Device Datasheet
  • Cyclone V SX, ST and SE SoC Device Errata
  • Documentation: Pin-Out Files for Intel FPGA Devices

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Document PDF Published Date Filter Doc Type Filter Collections Filter
Advanced Link Analyzer User Guide 2020-12-16 altera:content-area/device-configuration-and-remote-system-upgrades altera:document-type/user-guide
Embedded Peripherals IP User Guide 2020-12-23 altera:content-area/i-o-interfaces-protocols-and-signal-integrity,altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:intellectual-property,altera:development-software
Intel FPGA Software Installation and Licensing 2020-12-14 altera:document-type/reference-manual,altera:document-type/user-guide altera:development-software
10-Gbps Ethernet (10GbE) MAC IP Core Release Notes 2016-05-02 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/release-notes
ALTDQ_DQS2 IP Core User Guide 2017-05-08 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/user-guide
ALTERA_CORDIC IP Core User Guide 2017-05-08 altera:document-type/user-guide altera:intellectual-property
AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller 2017-09-22 altera:content-area/device-configuration-and-remote-system-upgrades altera:document-type/app-notes
AN 735: Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines 2015-05-04 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/app-notes
AN 736: Nios II Processor Booting From Altera Serial Flash (EPCQ) 2016-05-20 altera:document-type/app-notes
AN752: Guidelines for Handling Altera Wafer Level Chip Scale Package (WLCSP) 2015-11-02 altera:content-area/pcb-layout-and-packaging altera:document-type/app-notes
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide 2017-06-16 altera:content-area/clocking altera:document-type/user-guide altera:intellectual-property
Configuring Altera FPGAs 2014-12-15 altera:content-area/device-configuration-and-remote-system-upgrades altera:document-type/user-guide
Cyclone V Hard IP for PCI Express IP Core Release Notes 2016-10-31 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/release-notes
Cyclone V SoC Power Optimization 2015-02-09 altera:content-area/power-and-thermal-management altera:document-type/app-notes
Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide 2017-06-19 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/user-guide altera:intellectual-property
High-speed Reed-Solomon IP Core Release Notes 2017-11-06 altera:content-area/embedded-memory---dsp altera:document-type/release-notes altera:intellectual-property
Intel Quartus Prime Standard Edition Handbook Volume 2 Design Implementation and Optimization 2017-11-06 altera:document-type/user-guide altera:development-software
LDPC IP Core User Guide 2017-11-06 altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:intellectual-property
Nios II Embedded Design Suite Release Notes 2015-06-17 altera:document-type/release-notes,altera:document-type/design-guides
PCI Express Avalon -MM DMA Reference Design 2017-05-08 altera:document-type/app-notes
PowerPlay Early Power Estimator User Guide 2017-02-21 altera:content-area/power-and-thermal-management altera:document-type/user-guide altera:content-area/recommended-documents,altera:development-software
SDI Audio IP Cores Release Notes 2017-05-08 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/release-notes
Using the Altera PDN Tool to Optimize Your Power Delivery Network Design 2015-07-08 altera:content-area/power-and-thermal-management altera:document-type/app-notes
Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices 2015-12-04 altera:document-type/app-notes
Vision Processing with the Canny Edge Detection Reference Design 2015-02-14 altera:document-type/app-notes
Viterbi IP Core User Guide 2017-11-06 altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:intellectual-property
ALTIOBUF IP Core User Guide 2020-01-13 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/user-guide altera:intellectual-property
AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification 2018-09-01 altera:content-area/device-configuration-and-remote-system-upgrades altera:document-type/app-notes
AN 706: Routing HPS Peripheral Signals to the FPGA External Interface 2018-05-07 altera:document-type/app-notes altera:content-area/recommended-documents
AN 796: Cyclone V and Arria V SoC Device Design Guidelines 2020-07-27 altera:content-area/device-configuration-and-remote-system-upgrades,altera:content-area/development-kits altera:document-type/app-notes altera:intellectual-property,altera:content-area/recommended-documents,altera:development-software
ASMI Parallel II Intel FPGA IP Core Release Notes 2018-05-07 altera:content-area/device-configuration-and-remote-system-upgrades altera:document-type/release-notes
BCH Intel FPGA IP: User Guide 2018-11-30 altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:intellectual-property
Battery Management System Reference Design 2016-04-02 altera:document-type/reference-manual altera:development-software
Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide 2020-09-04 altera:content-area/device-configuration-and-remote-system-upgrades altera:document-type/user-guide
Creating Heterogeneous Memory Systems in Intel FPGA SDK for OpenCL Custom Platforms 2016-12-13 altera:content-area/external-memory-interface,altera:content-area/device-configuration-and-remote-system-upgrades,altera:content-area/embedded-memory---dsp altera:document-type/app-notes,altera:document-type/design-guides altera:development-software
Cyclone V Device Datasheet 2019-11-27 altera:content-area/external-memory-interface,altera:content-area/device-configuration-and-remote-system-upgrades,altera:content-area/clocking,altera:content-area/i-o-interfaces-protocols-and-signal-integrity,altera:content-area/embedded-memory---dsp,altera:content-area/power-and-thermal-management altera:document-type/data-sheets altera:collection/data-sheet,altera:content-area/recommended-documents
Cyclone V Device Handbook: Volume 1: Device Interfaces and Integration 2020-07-24 altera:content-area/external-memory-interface,altera:content-area/device-configuration-and-remote-system-upgrades,altera:content-area/clocking,altera:content-area/i-o-interfaces-protocols-and-signal-integrity,altera:content-area/embedded-memory---dsp,altera:content-area/power-and-thermal-management altera:document-type/user-guide altera:content-area/recommended-documents
Cyclone V Device Handbook: Volume 2: Transceivers 2018-10-24 altera:document-type/user-guide altera:content-area/recommended-documents
Cyclone V Hard Processor System Technical Reference Manual 2020-09-03 altera:content-area/hard-processor-system altera:document-type/reference-manual,altera:document-type/user-guide altera:content-area/recommended-documents
Cyclone V SX, ST and SE SoC Device Errata 2015-09-25 altera:document-type/errata-sheets altera:collection/data-sheet
Differences Among Intel SoC Device Families 2018-08-22 altera:content-area/external-memory-interface,altera:content-area/hard-processor-system altera:document-type/reference-manual,altera:document-type/user-guide altera:content-area/recommended-documents
Embedded Design Handbook 2020-07-22 altera:content-area/embedded-memory---dsp altera:document-type/design-guides,altera:document-type/user-guide altera:development-software
Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide 2020-03-11 altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:intellectual-property
FFT IP Core: User Guide 2017-11-06 altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:intellectual-property
Generic Nios II Booting Methods User Guide 2016-05-24 altera:content-area/external-memory-interface,altera:content-area/device-configuration-and-remote-system-upgrades altera:document-type/user-guide altera:intellectual-property,altera:development-software
Guidelines for Developing a Nios II HAL Device Driver 2015-06-12 altera:document-type/app-notes,altera:document-type/design-guides
HPS SoC Boot Guide - Cyclone V SoC Development Kit 2016-01-27 altera:content-area/development-kits altera:document-type/app-notes altera:intellectual-property,altera:development-software
High-speed Reed-Solomon IP Core User Guide 2017-11-06 altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:intellectual-property
Intel FPGA Software Installation and Licensing Quick Start 2018-11-26 altera:document-type/user-guide altera:development-software
Intel Quartus Prime Standard Edition Handbook Volume 1 Design and Synthesis 2018-05-09 altera:document-type/user-guide altera:development-software
Intel Quartus Prime Standard Edition Handbook Volume 3 Verification 2018-05-09 altera:document-type/user-guide altera:development-software
Intel SoC FPGA Embedded Development Suite (SoC EDS) Standard Version 20.1 Release Notes 2020-06-12 altera:content-area/hard-processor-system altera:document-type/release-notes altera:development-software
Intel SoC FPGA Embedded Development Suite User Guide 2020-08-07 altera:content-area/hard-processor-system altera:document-type/user-guide
LVDS SERDES Transmitter / Receiver IP Cores User Guide 2017-12-15 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/user-guide altera:intellectual-property
NCO IP Core: User Guide 2017-11-06 altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:intellectual-property
Nios II Processor Reference Guide 2020-10-22 altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:development-software
Reed-Solomon II IP Core User Guide 2016-05-02 altera:content-area/embedded-memory---dsp altera:document-type/user-guide altera:intellectual-property
Remote Update Intel FPGA IP Core Release Notes 2018-05-07 altera:content-area/device-configuration-and-remote-system-upgrades altera:document-type/release-notes
The Automotive-Grade Device Handbook 2019-08-27 altera:content-area/pcb-layout-and-packaging,altera:content-area/i-o-interfaces-protocols-and-signal-integrity,altera:content-area/power-and-thermal-management altera:document-type/user-guide
Unique Chip ID Intel FPGA IP Core Release Notes 2018-05-07 altera:content-area/device-configuration-and-remote-system-upgrades altera:document-type/release-notes
V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide 2018-07-31 altera:content-area/i-o-interfaces-protocols-and-signal-integrity altera:document-type/user-guide altera:intellectual-property
Power and Thermal Management
  • AN 734: Cyclone V SoC Power Optimization
  • Cyclone IV and Cyclone V PowerPlay Early Power Estimator
    (Please see EPE)
    PowerPlay Early Power Estimator User Guide
  • Achieving Lowest System Power with Low-Power 28-nm FPGAs
  • Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide
    Power Delivery Network (PDN) Tool 2.0 for Stratix® V, Arria® V, Arria II GZ, Cyclone V, and Cyclone IV Devices
    Power Delivery Network (PDN) Tool 2.0 for Arria 10 Devices
  • Device-Specific Power Delivery Network (PDN) Tool User Guide for Arria II/Stratix IV/Stratix III Device Families
    Power Delivery Network (PDN) Tool for Arria II GX Devices
    Power Deliver Network (PDN) Tool for Stratix IV Devices
    Power Delivery Network (PDN) Tool for Stratix III Devices
I/O Interfaces, Protocols and Signal Integrity
  • Cyclone V Hard IP for PCI Express User Guide
  • AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller
  • AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface
  • AN 653: Implementing the CPRI Protocol using the Deterministic Latency Transceiver PHY IP Core
    an653_Reference_Design_File
  • Cyclone V Avalon®-MM Interface for PCIe Solutions User Guide
  • Cyclone V Avalon-ST Interface for PCIe Solutions User Guide
  • V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
Embedded Memory
  • Increasing Efficiency with Hard Memory Controllers in Low-Cost 28 nm FPGAs (ver 1.1, Nov 2012, 577 KB)
DSP
  • Implementing Digital Processing for Automotive Radar Using SoCs (ver 1.3, Dec 2013, 758 KB)
Device Configuration and Remote System Upgrades
  • Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide
    user_led.zip (4 KB)
Design Guidelines
  • AN 662: Arria V and Cyclone V Design Guidelines
  • AN 676: Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices
    AN 676 Reference Design Example (1 MB)
  • Low-Cost Implementation of High-Performance PCIe Gen2 Hard IP (ver 1.1, Apr 2013, 313 KB)
  • Reducing Development Time for Advanced Medical Endoscopy Systems with an FPGA-Based Approach (ver 1.0, Aug 2012, 669 KB)
  • Tips and Techniques for 28-nm Design Optimization (ver 1.0, Nov 2011, 704 KB)
PCB Layout and Packaging
  • AN659: Thermal Management and Mechanical Handling for Lidless Flip Chip Ball-Grid Array
Development Kits
  • Product Catalog
  • Cyclone V E FPGA Development Board Reference Manual
  • Cyclone V E FPGA Development Kit User Guide
  • Cyclone V SoC Development Board Reference Manual
  • Cyclone V SoC Development Kit Reference Platform Porting Guide
  • Cyclone V GT FPGA Development Board Reference Manual
  • Cyclone V GT FPGA Development Kit User Guide
  • Cyclone V GX FPGA Development Board Reference Manual
  • Cyclone V GX FPGA Development Kit User Guide
End Applications
  • AN 717: Nios II Gen2 Hardware Development Tutorial
  • Driving Innovative Industrial Solutions (ver 1006-1.0, May 2013, 2 MB)
  • A Validated Methodology for Designing Safe Industrial Systems on a Chip (ver 1.3, Mar 2013, 371 KB)
  • Altera and Escape Communications' Microwave Modem Solution (ver 1.0, Feb 2014, 470 KB)
  • Altera's 28 nm Device Portfolio (ver 3.0, Apr 2014, 1 MB)
  • AN 425: Using the Command-Line Jam STAPL Solution for Device Programming
  • Broadcast Design Solutions from Altera (ver 2.0, May 2013, 443 KB)
  • Broadcast video and image processing (ver 2.1, Mar 2012, 411 KB)
  • Displays (ver 2.0, Mar 2012, 257 KB)
  • Optimize Motor Control Designs with an Integrated FPGA Design Flow (ver 1.2, May 2012, 811 KB)
  • Overcoming Smart Grid Equipment Design Challenges with FPGAs (ver 1.0, Feb 2013, 1 MB)
  • Reducing Development Time for Advanced Medical Endoscopy Systems with an FPGA-Based Approach (ver 1.0, Aug 2012, 669 KB)
General Device Documentation
  • Achieving Lowest System Power with Low-Power 28-nm FPGAs (ver 1.0, Mar 2012, 467 KB)
  • Intel's User-Customizable ARM-Based SoC FPGA (ver 1.4, Apr 2014, 6 MB)
  • Differences Among Intel SoC Device Families
  • Cyclone V FPGAs (ver 1.4, Aug 2014, 302 KB)
  • FPGA-Adaptive Software Debug and Performance Analysis (ver 1.0, May 2013, 717 KB)
  • Implementing Efficient Low-Power PCIe* Interfaces with Low-Cost FPGAs (ver 1.0, Feb 2013, 466 KB)
  • Industrial Motor Drive on a Single FPGA (ver 3.0, Mar 2013, 459 KB)
  • Integrating PLC Systems on a Single FPGA or SoC (ver 1.0, Nov 2013, 682 KB)
  • Low-Cost Implementation of High-Performance PCIe Gen2 Hard IP (ver 1.1, Apr 2013, 313 KB)
  • Reducing Total System Cost with Low-Power 28-nm FPGAs (ver 1.1, Apr 2012, 517 KB)

Related Links

  • Intel SoC FPGA Overview
  • Architecture Matters
  • SoC FPGA Resource Guide