The HardCopy® Series Handbook includes the data sheets for HardCopy II ASICs and earlier HardCopy families. Additional chapters cover hardware design considerations and software support. To view the entire handbook, click the link below.
Check the Knowledge Database for Known Issues with HardCopy Stratix® devices in the Handbook.
HardCopy Series Handbook (2 MB)
HardCopy Series Handbook, Volume 1 (ver 4.5, Sep 2008, 2 MB)
Section I. HardCopy Stratix Device Family Data Sheet
- Chapter 1. Introduction to HardCopy Stratix Devices (ver 2.4, Sep 2008, 93 KB)
- Chapter 2. Description, Architecture & Features (ver 3.4, Sep 2008, 156 KB)
- Chapter 3. Boundary-Scan Support (ver 3.4, Sep 2008, 104 KB)
- Chapter 4. Operating Conditions (ver 3.4, Sep 2008, 261 KB)
- Chapter 5. Quartus II Support for HardCopy Stratix Devices (ver 3.4, Sep 2008, 647 KB)
- Chapter 6. Design Guidelines for HardCopy Stratix Performance Improvement (ver 1.4, Sep 2008, 304 KB)
Section II. HardCopy APEX Device Family Data Sheet
- Chapter 7. Introduction to HardCopy APEX Devices (ver 2.3, Sep 2008, 87 KB)
- Chapter 8. Description, Architecture & Features (ver 2.3, Sep 2008, 113 KB)
- Chapter 9. Boundary-Scan Support (ver 2.3, Sep 2008, 91 KB)
- Chapter 10. Operating Conditions (ver 2.3, Sep 2008, 255 KB)
Section III. General HardCopy Series Design Considerations
- Chapter 11. Design Guidelines for HardCopy Series Devices (ver 3.4, Sep 2008, 265 KB)
- Chapter 12. Power-Up Modes & Configuration Emulation in HardCopy Series Devices (ver 2.5, Sep 2008, 345 KB)
Section IV. HardCopy Design Center Migration Process
- Chapter 13. Back-End Design Flow for HardCopy Series Devices (ver 1.4, Sep 2008, 148 KB)
- Chapter 14. Back-End Timing Closure for HardCopy Series Devices (ver 2.4, Sep 2008, 274 KB)
Related Documentation by Document Types
User Guides
- HardCopy II Clock Uncertainty Calculator User Guide (ver 1.0, Aug 2007, 611 KB)
Application Notes
- AN 432: Using Different PLL Settings Between Stratix II and HardCopy II Devices (ver 1.2, Mar 2010, 149 KB)
- AN650: Initializing the UniPHY Nios II Sequencer in HardCopy Devices using FPP Configuration Scheme (ver 1.0, Oct 2011, 500 KB)
- AN 545: Design Guidelines and Timing Closure Techniques for HardCopy ASICs (ver 2.1, Jul 2010, 2 MB)
- AN 550: Using the DLL Phase Offset Feature in Stratix FPGAs and HardCopy ASICs (ver 2.0, Mar 2010, 547 KB)
- AN 554: How to Read HardCopy PrimeTime Timing Reports (ver 2.0, Mar 2010, 554 KB)
- AN 477: Designing RGMII Interface with FPGA and HardCopy Devices (ver 2.0, Jan 2010, 519 KB)
- AN 311: ASIC-to-FPGA Design Methodology and Guidelines (ver 3.1, Apr 2009, 286 KB)
- AN 453: HardCopy II Fitting Techniques (ver 2.0, Nov 2008, 716 KB)
Errata Sheets
- HardCopy Stratix Device Errata Sheet (ver 1.0, Feb 2005, 55 KB)
Product Overview
- Altera FPGAs for radar and advanced sensors (ver 1.0, Oct 2007, 219 KB)
Process Change Notifications
- PCN 1408 Transfer of Wafer Bump Operations (ver 1.0, Feb 2015, 116 KB)
Inserts and Advertorials
- HardCopy Structured ASIC (ver 1.0, Feb 2006, 1 MB)
Related Documentation by Solutions
External Memory Interfaces
- AN 550: Using the DLL Phase Offset Feature in Stratix FPGAs and HardCopy ASICs (ver 2.0, Mar 2010, 547 KB)
altmemphy_ext_dll.zip (48 KB)
altmemphy_int_dll.zip (47 KB)
static_dll.zip (18 KB)
- AN650: Initializing the UniPHY Nios II Sequencer in HardCopy Devices using FPP Configuration Scheme (ver 1.0, Oct 2011, 500 KB)
an650_UniPHY_HCX_Migration_Reference_Design.zip (2 MB)
I/O Interfaces, Protocols and Signal Integrity
- AN 477: Designing RGMII Interface with FPGA and HardCopy Devices (ver 2.0, Jan 2010, 519 KB)
Design Guidelines
- AN 432: Using Different PLL Settings Between Stratix II and HardCopy II Devices (ver 1.2, Mar 2010, 149 KB)
- AN 311: ASIC-to-FPGA Design Methodology and Guidelines (ver 3.1, Apr 2009, 286 KB)
- AN 453: HardCopy II Fitting Techniques (ver 2.0, Nov 2008, 716 KB)
- AN 477: Designing RGMII Interface with FPGA and HardCopy Devices (ver 2.0, Jan 2010, 519 KB)
- AN 545: Design Guidelines and Timing Closure Techniques for HardCopy ASICs (ver 2.1, Jul 2010, 2 MB)
Example_design.zip (578 KB)
- HardCopy II Clock Uncertainty Calculator User Guide (ver 1.0, Aug 2007, 611 KB)
HCII_Clock_Uncertainty_Calculator.zip (1,005 KB)
End Applications
- Automotive-Grade Device Handbook (ver 1.0, Feb 2008, 844 KB)
- Altera FPGAs for radar and advanced sensors (ver 1.0, Oct 2007, 219 KB)
General Device Documentation
- Altera FPGAs for radar and advanced sensors (ver 1.0, Oct 2007, 219 KB)
- HardCopy Structured ASIC (ver 1.0, Feb 2006, 1 MB)