Intel provides boundary-scan description language (BSDL) files for IEEE Standard 1149.1, IEEE Standard 1149.6 and IEEE Standard 1532 specifications. BSDL files provide a syntax that allows the device to run boundary-scan test (BST) and in-system programmability (ISP). The IEEE 1149.1 BSDL files available on this website are used for pre-configuration BST. If you want to perform BST after configuration, you can select the appropriate generation tools and guidelines for the post-configuration BSDL generation in Table 1.
BSDL Support
Table 1. BSDL File Generation Tools and Guidelines
| Tools or Guidelines | FPGA | CPLD | Configuration Devices |
|---|---|---|---|
| BSDL Customizer | Stratix®, Stratix® GX, Stratix® II, Stratix® II GX, Stratix® III Arria® GX Cyclone®, Cyclone® II, Cyclone® III |
MAX® 3000, MAX® 7000, MAX® II |
EPC |
| Stratix® IV, Stratix® V Arria® II, Arria® V Cyclone® III LS, Cyclone® IV, Cyclone® V |
MAX® V | - |
|
| Post-Configuration BSDL Generator | - | MAX® V | - |
| Post-Configuration BSDL Creator | Intel® Stratix® 10 | - |
- |
| Post-Configuration BSDL Generator | Intel® Arria® 10 | - |
- |
| Post-Configuration BSDL Creator | Intel® MAX® 10 | - | - |
| Post-Configuration BSDL Generator |
Intel® Cyclone® 10 LP, Intel® Cyclone® 10 GX | - | - |
| Post-Configuration BSDL Generator | Intel® Agilex® | - | - |
Downloads
- IEEE 1149.1 BSDL Files
- IEEE 1149.6 BSDL Files
- IEEE 1532 BSDL Files
- Basic Boundary-Scan Test Troubleshooting Guideline (PDF)
- FAQs (PDF)
- Preconfig BSDL Customizer (ZIP)
Related Documents
- AN 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera® Devices (PDF)
- IEEE 1149.1 (JTAG) Boundary-Scan Testing for MAX® II Devices (PDF)
- JTAG and In-System Programmability in MAX® V Devices (PDF)
- IEEE 1149.1 (JTAG) Boundary Scan Testing for Cyclone® II Devices (PDF)
- IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix® II and Stratix® II GX Devices (PDF)
- IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix® III Devices (PDF)
- JTAG Boundary Scan Testing in Stratix® IV Devices (PDF)
- IEEE 1149.1 (JTAG) Boundary Scan Testing for Cyclone® III Devices (PDF)
- IEEE 1149.1 (JTAG) Boundary Scan Testing for Arria® GX Devices (PDF)
- JTAG Boundary Scan Testing in Arria® II Devices (PDF)
- MorphIO: An I/O Reconfiguration Solution for Altera® Devices White Paper (PDF)