Digital set-top boxes (DSTBs) receive and decode television broadcasts from satellite, cable, and/or terrestrial sources. Integrated digital televisions (DTVs) have built-in digital tuners, demodulators, and source decoders, so they do not require digital set-top boxes that receive digital broadcasts.
Traditional DSTBs are designed to receive standard definition (SD) Moving Pictures Experts Group-2 (MPEG-2) video format broadcasts. However, many of today’s DSTBs are high-definition (HD)-ready. In fact, selected cable television service providers, networks, and local terrestrial TV stations are concurrently transmitting both SD and HD content. Over time, MPEG-4 will displace the MPEG-2 format for both SD and HD.
When MPEG-4 becomes the standard compression standard, systems implementing reprogrammable logic devices (such as Intel® FPGAs) will be able to seamlessly upgrade without having to scrap inventory items or make new hardware. Using FPGAs, manufacturers can design a STB that can decode MPEG-2 video format, and then later upgrade that same STB for MPEG-4 by simply reprogramming the FPGA in-system.
High-end DSTBs usually offer personal video recorder (PVR) and/or an HD DVD recorder for Blu-ray functions. Microcontrollers in DSTBs or integrated DTVs can perform a number of functions for these systems, including control panel management and on-screen display (OSD).
Many current DSTBs can be classified either as free to air (FTA) or pay TV versions. A pay TV example would be DSTBs designed for DirecTV or Dish Network (in the USA), which require conditional access to decode the audio and video.
DSTB manufacturers typically design the PCBs for both low-end and high-end DSTB systems and require a flexible solution for implementing their various designs. The Figure below shows a typical Intel programmable logic device (PLD) solution for DSTBs and depicts one of the wide range of applications that are possible with an FPGA-based solution.
Example of an Intel PLD Solution for DSTBs and DTVs
Some examples of Intel or third-party intellectual property (IP) used in DSTBs and DTVs include:
Intel’s low-cost Cyclone® III, MAX® II, and MAX 3000A devices provide cost-effective programmable solutions for audio and video processing, making these devices ideal for digital video applications. The Cyclone FPGA series and the MAX CPLD series also contain system functions that complement available ASSPs, such as on-screen display (OSD) and timing display.
Cyclone® III FPGAs are built on a 65-nm low power (LP) process technology. The Cyclone III family is comprised of eight devices ranging from 5K to 120K logic elements (LEs) and up to 534 user I/O pins. Cyclone III FPGAs offer up to 4 Mbits of embedded memory, 288 embedded 18x18 multipliers, dedicated external memory interface circuitry, and phase-locked loops (PLLs) making them ideal for high-end video and image processing functions.
The Intel Nios® II family of embedded processors can be implemented in Cyclone series devices for high-performance, cost-efficient processing solutions. The Cyclone series and its solutions offer digital video designers unparalleled capability at extremely affordable pricing.
Intel’s MAX CPLD series is the industry’s most successful and widely used CPLDs. MAX 3000A devices are optimized for high-volume, cost-sensitive applications. Intel’s latest CPLDs, MAX II devices, are designed for low-cost and low-power applications. The non-volatile and low-cost features of the MAX 3000A and MAX II devices make them ideal for DVD player/recorder functions such as address decoding, system timing, and system bug fixes.
Typical LCD TV Interface Block Diagram
Flat panel displays (LCDs, plasma display panels, plasma low-profile, and liquid crystal on silicon) and video projectors receive, decode, and display digital video streams from a variety of sources. As prices of flat panel TVs decrease, they are becoming more common in consumer households.
The heart of the LCD HDTV is its image processing and timing control block. The image processing block typically includes functions such as scan rate converter, frame rate converter, color decoder, motion detection, scalar, and de-interlacing.
The color response time of an HDTV LCD display is slower than a conventional display, and depends on the color content. This challenges the development of image-processing algorithms when the additional requirement to eliminate any viewing artifact is factored in. FPGA design flexibility offers a significant advantage, allowing you to redesign the algorithm within the device without having to reprogram it.
Once the data has been processed, the video board interfaces to the LCD column and row drivers through a LVDS bus or a Reduced Swing Differential Signaling (RSDS) bus running up to 400 Mbps.
Altera offers a broad portfolio of intellectual property (IP) cores for display applications. The IP cores include, embedded processors, video and Image processing functions, standard interfaces, and peripherals. You can add proprietary logic to this wide portfolio of IP cores to develop unique solutions in a timely fashion. You can obtain these IP cores either directly from Altera or from third-party IP partners. All the IP cores are thoroughly tested and optimized for Altera® products. Some of the video display related IP from Altera include:
Altera and its partners also offer development kits to accelerate the flat panel display design process. These kits based on Altera’s FPGAs allow display designers and ASSP vendors to add next-generation picture enhancement features to their products as market demands evolve, rather than being tied to lengthy ASIC development cycles.
Altera’s low-cost Cyclone III and MAX® II devices provide the most cost-effective programmable solution for A/V processing, making these devices ideal for digital video applications. Cyclone series FPGAs and MAX series CPLDs also contain system functions that complement available ASSPs, such as OSD and timing display.
Cyclone III FPGAs are built on a 65-nm, low-power process technology. The Cyclone III family includes eight devices ranging from 5K to 120K logic elements (LEs) and up to 534 user I/O pins. Cyclone III FPGAs offer up to 4 Mbits of embedded memory, 288 embedded 18 x 18 multipliers, dedicated external memory interface circuitry, and phase-locked loops (PLLs) making them ideal for high-end video and image processing functions. Additional features include high-speed differential signal I/O capabilities to enable LVDS and RSDS interfaces used in flat panel displays.
Altera’s MAX devices are the industry’s most successful and widely used CPLD solutions. Altera’s latest CPLDs, MAX II devices, are designed for low-cost and low-power applications. The non-volatile and low-cost features of the MAX II devices make them ideal for display functions such as address decoding, system timing, and system bug fixes.
Interfaces Support in Cyclone FPGAs
Blu-ray players and recorders play back decompressed and record compressed high-quality digital video and audio. High-end Blu-ray player/recorder systems also include advanced audio and video processing capabilities for recording digital TV signals. When a Blu-ray player/recorder system includes a CD-RW drive, an integrated drive electronics (IDE) conversion is needed to interface with the video bus. The actual interface to the Blu-ray drive is the AT attachment package interface (ATAPI). ATAPI provides the additional commands needed for controlling a CD-ROM or Blu-ray player so that your computer can use the IDE interface and controllers to control these types of devices. The microcontroller of a Blu-ray player/recorder performs a number of system functions, including control panel management and post video/audio processing. The following figure shows an example Blu-ray player/recorder system using Intel® devices.
Intel’s low-cost Cyclone® III and MAX® II, and MAX 3000A devices provide cost-effective programmable solutions for audio and video processing, making these devices ideal for digital video applications. Cyclone series FPGAs and MAX series CPLDs also contain system functions that complement available ASSPs, such as on-screen display (OSD) and timing display.
Cyclone III FPGAs are built on a 65-nm, low-power process technology. The Cyclone III family is comprised of eight devices ranging from 5K to 120K logic elements (LEs) and up to 534 user I/O pins. Cyclone III FPGAs offer up to 4 Mbits of embedded memory, 288 embedded 18x18 multipliers, dedicated external memory interface circuitry, and phase-locked loops (PLLs) making them ideal for high-end video and image processing functions. Cyclone III FPGAs and their solutions offer digital video designers unparalleled capability at extremely affordable pricing.
Intel’s MAX devices are the industry’s most successful and widely used CPLD solutions. MAX 3000A devices are optimized for high-volume, cost-sensitive applications. Intel’s latest CPLDs, MAX II devices, are designed for low cost and low power applications. The non-volatile and low-cost features of the MAX 3000A and MAX II devices make them ideal for Blu-ray player/recorder functions such as address decoding, system timing, and system bug fixes.
Portable applications, also known as mobile devices, include many types of consumer handheld devices such as mobile handsets, smartphones, mobile Internet devices, portable media players, electronics toys/games, portable navigators, and digital camera/camcorders. Despite the economic downturn at the end of 2008, industry analysts predict demand for mobile devices and consumer electronics will continue to rise. The largest growth areas for mobile devices will be in mobile Internet devices, smartphones, and portable navigation.
Prepared to address this market trend, Intel introduced the MAX® IIZ CPLD, targeting low-power, low-cost handheld devices. Different from other markets, portable applications require a silicon solution with low power (for battery life-extension), low cost (typically $2 or less), and small packages (such as 5 x 5 mm or less). Designed with the market requirements of portable devices in mind, Intel's MAX IIZ devices consume almost zero power in standby mode, cost $2 or less in high-volume, and have a very small package size (package options for the smallest device can be less than 5 x 5 mm), making it one of the most attractive CPLD solutions in the market.
Because of its low power, low cost, and small package features, you can use a MAX IIZ device as a companion device to an ASSP or ASIC to help manage system processor power consumption or system boot-up sequencing. Other typical uses include I/O expansion, voltage level shifting, capacitive touch sensors, touch-screen encoders, key board decoders, color LED drivers, interrupt handling, or data processing. A unique feature only offered by MAX IIZ devices allows users to write security code into its internal user flash memory (up to 8 Kbytes). The following figure illustrates typical uses for MAX IIZ CPLDs in portable applications.
The following figure shows an example of a MAX IIZ CPLD managing a portable device's system power. In this example, the MAX IIZ device takes 60 micro-seconds for a fast system boot up and reduces system power consumption with minimal standby current (29uA). With a wide-range of I/O voltage variation (1.5V, 1.8V, 2.5V, 3.3V), it can also function as three voltage level shifters. Its small package allows for a high system integration, and its programmability enables you to make last minute changes to the design. You can find more examples of using MAX IIZ devices in portable applications on the MAX II and MAX IIZ CPLD Design Examples web page.
Graphical LCD touch-screens are increasing prevalent in many portable applications, gradually replacing mechanical push buttons for a more contemporary, sophisticated human-machine interface (HMI). More recent implementations of touch technology utilize “multitouch” where you can use two fingers to manipulate an object, as on Apple’s iPhone.
Unlike ASSPs, MCUs, or other competitive technologies, MAX IIZ CPLDs deliver high I/O counts, ease of use, low power, low cost, small package, and the flexibility needed to implement a single or multitouch display for portable devices. The followin figure shows a two-chip solution for multitouch design: the Analog Devices AD7142 integrated capacitance-to-digital converter and a MAX IIZ EPM240Z CPLD to expand the AD7142’s capability to handle two-dimensional ITO glass or film.
In addition to MAX IIZ devices, Intel also offers MAX II and MAX IIG CPLDs as well as the low-cost Cyclone® FPGA family, including Cyclone III FPGAs. Different from non-volatile CPLDs, FPGAs have built-in RAM, which allows them to perform digital signal processing (DSP) functions such as signal processing, image enhancement, or acting as the system's CPU.
The following figure shows an example of FPGA use in a smartphone or mobile Internet device.
In a typical portable media player system (see the following figure), the central functional block is the image processing controller. The basic functions required for the image processing controller can typically be implemented either in a digital signal processor or an ASIC/ASSP, but a companion PLD is often incorporated to allow for feature enhancements to enable a developer’s product differentiation strategy. The high pin counts and programmable features of CPLDs make them ideal devices for interface bridging between data formats or IO expansion when adding advanced features that are not available on the base platform.
CPLDs have also traditionally been used for board-level power management, voltage-level shifting, and DSP configuration functions. For portable systems, CPLDs maximize the system battery life by shutting down unused ICs in the system.
Finally, the non-volatile nature of CPLDs provides a way for developers to implement security functions for protection of content, user-specific information, and intellectual property (IP).
Portable edutainment toys are educational toys that both teach and entertain children. The demand for these types of toys is growing because today's parents prefer toys that not only entertain but educate their children.
In a typical portable edutainment toy system (see the following figure), the central functional block is the signal conditioning controller. The signal conditioning controller positions the motor based on inputs from an external sensor, processes and loads images to the display panel, handles audio processing functions such as audio tone synthesis, and manages external audio sources. Because these three functions are unique to the system specifications of the end product, a CPLD implementation provides a combination of benefits, including maximum design flexibility, low risk, and fastest time-to-market.
Similar to the portable media player application, CPLDs are ideal for interface bridging, I/O expansion, power management, voltage-level shifting, digital signal processing (DSP) configuration, and clock generation functions.
Touch technology has changed from a touch point to a 2D touch area. The most common 2D touch applications are PC navigation touch pads and LCD touch screens. MAX® IIZ CPLDs are ideal for touch-pad and touch-screen solutions and for integrating capacitive touch switches into products.
Single touch point solutions have been available for years. Single point solutions are traditionally implemented with resistive or capacitive 4-wire Iridium-Tin-Oxide (ITO) screen overlays. These touch screen solutions are limited to decoding a single point at a time and two or more touches are incorrectly interpreted. In addition, the solutions are analog and require sophisticated analog electronics for accurate decoding. MAX IIZ devices offer an all digital alternative, using a digital resistive ITO touch screen.
The Altera® digital touch reference design decodes all single and two-point touch patterns and can decode many 3, 4, and 5 point patterns. The digital touch-screen controller reference design converts the 30-pin touch screen output to industry standard serial interface output. MAX IIZ devices allow easy modification of the design to accommodate proprietary serial or parallel interfaces. The MAX IIZ Digital Touch Screen Development board (available in Q1 '09) includes a MAX IIZ controller card, 5.7” Digital SmartTouch screen, and a 4” digital touch pad.
A multitouch screen or pad takes the flexibility of a user interface to a new level. The Altera multitouch reference design can interpret an unlimited number of simultaneous touch points. The reference design works with up to a 14-cm x 16-cm capacitive touch pad or capacitive touch screen. The 2D multitouch reference design is based on a MAX IIZ EPM240Z CPLD and an Analog Devices AD7142 integrated capacitance-to-digital converter (CDC).
The AD7142 device, which senses the capacitance variant of the ITO sensor board, has only 14 capacitance sensor channels. In our reference design, the MAX IIZ CPLD expands the AD7142 device's capability to handle a two-dimensional ITO glass or film (see Multitouch Diagram below). The application processor uses I2C (see Touch Points Diagram below) to access the CDC register file of the AD7142 device and sets the MAX IIZ CPLD to drive the SRC signal to the appropriate axle.
The reference design uses SPI or I2C to access the CDC register file of the AD7142 device and sets the MAX IIZ CPLD to select which column of the touch sensor is being actively scanned. The MAX IIZ CPLD also generates an interrupt signal when the touch screen first senses a touch after a long pause. The MAX IIZ CPLD enhances the ability of the AD7142 to sense a 1 x 14 array of capacitive touch points to a 16 x 14 array of sense points.
The Altera reference design offering provisions for power-down or sleep modes. The first level of sleep is obtained by the application processor reducing the sample rate. The application processor can also sample subset horizontal and vertical traces, and use the accuracy of the AD7142 device to interpolate touches between active traces. The maximum power savings is achieved when the application processor is powered down, and the MAX IIZ CPLD implements a very power-efficient capacitance detection system to sense when the screen is touched. Once the CPLD detects a touch, it can wake the processor using an interrupt signal. Once awake, the system can properly read the touch location.