AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 4/01/2024
Public
Document Table of Contents

2.3. Intel® FPGA Device Features

Agilex™ 7 Device Features

Table 3.   Agilex™ 7 Device Features
Performance 1 Built on Intel® 10nm SuperFin technology with second generation Hyperflex® architecture with enhanced fabric resources, high-speed routing, and improved clocking infrastructure, Agilex™ 7 devices average 50% higher performance compared to the previous generation Stratix® 10 FPGA and SoC devices.
Power 1 With metal stack optimizations specific for FPGAs, a lower minimum voltage, and extensive transistor-level tuning, Agilex delivers up to 40% lower power compared to Stratix® 10 devices.
Transceivers The Agilex™ 7 FPGA and SoC family delivers accelerated transceiver innovation with data rates up to 116Gbps and support for PCI Express* up to Gen 5. Agilex™ 7 FPGA and SoC devices come with a comprehensive portfolio of transceiver tiles.
Floating-point operations The Agilex™ 7 FPGA and SoC family offers a configurable DSP engine which features hardened support for both floating-point and fixed-point operations such as single-precision FP32, half-precision FP16, BFLOAT16, and INT8 calculations. This programmability, coupled with the innovations in the DSP blocks is ideal for evolving AI workloads.
Processor Highly efficient quad-core Arm* Cortex* -A53 processor cluster optimized for ultra-high performance per watt.
Applications Agilex™ 7 FPGAs and SoCs enable next-generation, high-performance applications in the data center, networking, and the edge.

Stratix® 10 Device Features

Table 4.   Stratix® 10 Device Features
Performance Built on the Intel® 14 nm Tri-Gate process, Stratix® 10 devices deliver 2X core performance gains over previous-generation, high-performance FPGAs. 2
Power Reduced IP size, enabled by the Hyperflex® FPGA Architecture allows the consolidation of designs that span multiple devices into a single device, reducing power by up to 70% versus previous-generation high-performance FPGAs.2
Transceivers Stratix® 10 FPGA and SoC devices take advantage of heterogeneous 3D system-in-package (SiP) technology to integrate a monolithic FPGA core fabric with 3D SiP transceiver tiles and other advanced components in a single package.
Floating-point operations The hardened floating-point operators within each DSP block, initially introduced in the Arria® 10 device family, are extended to deliver an order of magnitude greater throughput in Stratix® 10 FPGA and SoC devices.

Digital signal processing (DSP) designs can achieve up to 10 tera floating point operations per second (TFLOPS) of IEEE 754 single-precision floating-point operations.

Processor Next-generation hard processor system (HPS), quad-core Arm* Cortex* -A53 processor cluster that results in high-perfomance and power-efficient SoC devices.2
Applications Address challenges in high-performance systems in the most demanding applications including communications, data center acceleration, high-performance computing, radar processing, ASIC prototyping, and many more.

Arria® 10 Device Features

Table 5.   Arria® 10 Device Features
Performance A speed grade faster core performance and up to a 20% fMAX advantage compared to the competition, using publicly-available Intel® FPGA IP Evaluation Mode designs.
Power Arria® 10 FPGAs and SoCs are up to 40 percent lower power than previous generation FPGAs and SoCs
Industry’s only
  • Hard floating-point digital signal processing (DSP) blocks with speeds up to 1.5 tera floating-point operations per second (TFLOPS)3
  • 20 nm ARM-based SoC
Applications FPGAs and SoCs deliver the integration needed to address a wide range of applications for many industries, including communications, defense, broadcast, high-performance computing, test, and medical

Cyclone® 10 GX Device Features

Table 6.   Cyclone® 10 GX Device Features
Industry’s first Low-cost FPGA with IEEE 754-compliant hard floating-point DSP blocks
Applications Optimized for high-bandwidth, performance applications such as Industrial Vision, Robotics, and Automotive Infotainment.
1 For configuration details for performance and power improvement values, refer to https://intel.com/performanceindex.
2 Comparison based on Stratix® V vs. Stratix® 10 using Quartus® Prime Pro Edition 16.1 Early Beta. Stratix® V Designs were optimized using 3 step optimization process of Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization in order to utilize Stratix® 10 architecture enhancements of distributed registers in core fabric. Designs were analyzed using Quartus Prime Pro Fast Forward Compile performance exploration tool. For more details, refer to HyperFlex FPGA Architecture Overview White Paper: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01220-hyperflex-architecture-fpga-socs.pdf. Actual performance users achieve varies based on level of design optimization applied. Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration affect actual performance. Consult other sources of information to evaluate performance as you consider a purchase. For more complete information about performance and benchmark results, visit https://intel.com/performanceindex.
3 Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit https://intel.com/performanceindex. Performance comparison methodology and detailed results documented in the Arria® 10 Performance Benchmarking Methodology and Results white paper available at the The Intel FPGAs and Programmable Devices Arria 10 Performance page .