AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

ID 683539
Date 1/05/2021
Public
Document Table of Contents

1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

Updated for:
Intel® Quartus® Prime Design Suite 20.4

This document describes reset design techniques to ensure reliable power-up, reset release conditions, and maximum performance on Intel® Hyperflex™ architecture FPGAs. Proper application of reset design techniques allows you to take full advantage of the Hyper-Pipelining and Hyper-Retiming performance optimization features in Intel® Stratix® 10 and Intel® Agilex™ devices.

Refer to the following reset recommendations, strategies, and recommended coding techniques for effective reset implementation: