AN 831: Intel® FPGA SDK for OpenCL™: Host Pipelined Multithread

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ID 683013
Date 11/20/2017
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Host Pipelined Multithread
1. Intel® FPGA SDK for OpenCL™ Host Pipelined Multithread x
1.1. Introduction 1.2. Pipelining Framework for High Throughput Design 1.3. Optimization Techniques for CPU Tasks 1.4. Design Example: Data Compression Algorithm 1.5. Document Revision History
1.3. Optimization Techniques for CPU Tasks x
1.3.1. Processor Affinity or CPU Pinning 1.3.2. Cache Optimizations
1.4. Design Example: Data Compression Algorithm x
1.4.1. Host Channel Streaming Feature 1.4.2. Pipelining Framework Details 1.4.3. Fine Tuning the Framework Design 1.4.4. Performance Evaluation
1.4.3. Fine Tuning the Framework Design x
1.4.3.1. Huffman Code (Tree) Generation 1.4.3.2. Processor Affinity in GZIP
1. Intel® FPGA SDK for OpenCL™ Host Pipelined Multithread

1.4.4. Performance Evaluation

Intel has tested this framework on different benchmarks and by providing multiple input files. It was observed that the system throughput is same as the kernel throughput or even better.

The kernel throughput is greater than 3 GB/s for input files larger than 130 MB. This result determines that the design is very competitive for RTL design, and more powerful when compared to the CPU alone.

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