Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP Cores Release Notes

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1. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP Cores Release Notes
1. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP Cores Release Notes x
1.1. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.4.1 1.2. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.4.0 1.3. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.2.1 1.4. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.2.0 1.5. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.1.1 1.6. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.1.0 1.7. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.0.0 1.8. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v19.2.0 1.9. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v19.1 1.10. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v18.1 1.11. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v18.0
1.1. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.4.1 x
1.1.1. RAM: 2-PORT Intel® FPGA IP v20.4.1
1.2. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.4.0 x
1.2.1. RAM: 2-PORT Intel® FPGA IP v20.4.0
1.3. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.2.1 x
1.3.1. ROM: 1-PORT Intel® FPGA IP v20.2.1
1.4. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.2.0 x
1.4.1. ROM: 1-PORT Intel® FPGA IP v20.2.0 1.4.2. RAM: 2-PORT Intel® FPGA IP v20.2.0
1.5. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.1.1 x
1.5.1. RAM: 1-PORT Intel® FPGA IP v20.1.1 1.5.2. RAM: 4-PORT Intel® FPGA IP v20.1.1 1.5.3. ROM: 2-PORT Intel® FPGA IP v20.1.1
1.6. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.1.0 x
1.6.1. RAM: 1-PORT Intel® FPGA IP v20.1.0 1.6.2. RAM: 2-PORT Intel® FPGA IP v20.1.0 1.6.3. RAM: 4-PORT Intel® FPGA IP v20.1.0 1.6.4. ROM: 1-PORT Intel® FPGA IP v20.1.0 1.6.5. ROM: 2-PORT Intel® FPGA IP v20.1.0
1. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP Cores Release Notes

1.6.4. ROM: 1-PORT Intel® FPGA IP v20.1.0

Table 21.  v20.1.0 2020.10.12
Quartus® Prime Version Description Impact
20.3

Removed support for Use Stratix M512 emulation logic cell style for the LCs memory block type in the Stratix® 10 and Agilex™ 7 devices.

You are required to either change to default logic cell style or switch to non-LCs memory block type in the Stratix® 10 and Agilex™ 7 devices.
Added "X" propagation support in simulation model for the Stratix® 10 devices. —
Table 22.  v20.1.0 2020.08.03
Quartus® Prime Version Description Impact
20.1 Enabled the In-System Memory Content Editor (ISMCE) support in the Agilex™ 7 devices. This change is optional. If you do not upgrade your IP, it does not have this new feature.
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