AN 684: 100 Gbps CFP2 Design with Stratix V GT FPGAs

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ID 683219
Date 1/16/2014
Public
Document Table of Contents
Document Table of Contents x
1. Design Guidelines for 100 Gbps - CFP2 Interface
1. Design Guidelines for 100 Gbps - CFP2 Interface x
1.1. Stratix V GT Transceiver Channels 1.2. CFP2 Host Connector Assembly and Pinout 1.3. Stratix V GT to CFP2 Interface Layout Design 1.4. BGA Breakout Optimization 1.5. CFP2 Interface Optimization 1.6. Example Design Channel Performance 1.7. Document Revision History
1.3. Stratix V GT to CFP2 Interface Layout Design x
1.3.1. Board Stack Up Dimensions
1.6. Example Design Channel Performance x
1.6.1. Simulation Results for Stratix V GT to CFP2 Connector Layout Design
1. Design Guidelines for 100 Gbps - CFP2 Interface

1.7. Document Revision History

Table 1.  Document Revision History
Date Version Changes
January 2014 2014.01.16
  • Changed "Ansoft HFSS" to "Ansys HFSS".
  • Updated HFSS definition to High Frequency Structural Simulator.
  • Updated Simulation Results for Stratix V GT to CFP2 Connector Layout section to clarify that HFSS is used for the simulation.
March 2013 2013.03.29 Initial release.
Level Two Title