Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

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ID 683236
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Design Compilation 3. Reducing Compilation Time 4. Intel® Quartus® Prime Pro Edition User Guide Design Compilation Archives A. Intel® Quartus® Prime Pro Edition User Guides
2. Design Compilation x
2.1. Compilation Overview 2.2. Using the Compilation Dashboard 2.3. Design Netlist Infrastructure 2.4. Using the Node Finder 2.5. Analysis & Elaboration Flow 2.6. Design Synthesis 2.7. Design Place and Route 2.8. Incremental Optimization Flow 2.9. Fast Forward Compilation Flow 2.10. Full Compilation Flow 2.11. Compilation Monitoring Mode 2.12. Exporting Compilation Results 2.13. Integrating Other EDA Tools 2.14. Compiler Optimization Techniques 2.15. Synthesis Language Support 2.16. Synthesis Settings Reference 2.17. Fitter Settings Reference 2.18. Design Compilation Revision History
2.1. Compilation Overview x
2.1.1. Compilation Flows 2.1.2. Compilation Hierarchy 2.1.3. Compilation on a Compute Farm
2.3. Design Netlist Infrastructure x
2.3.1. DNI Netlist Five-Box Data Model
2.5. Analysis & Elaboration Flow x
2.5.1. Exploring the RTL Analyzer 2.5.2. Use Case Examples
2.5.1. Exploring the RTL Analyzer x
2.5.1.1. Sweep Hints Viewer 2.5.1.2. Object Set Console 2.5.1.3. Module Interfaces 2.5.1.4. Bundled Instances 2.5.1.5. Auto-hide Unconnected Pins 2.5.1.6. Filtering Ports and Nets 2.5.1.7. Expand Connections
2.5.2. Use Case Examples x
2.5.2.1. Scripting Routine Tasks Using Tcl Commands 2.5.2.2. Traversing the Design Netlist Using Tcl Commands
2.6. Design Synthesis x
2.6.1. Preparing for Design Synthesis 2.6.2. Running Synthesis 2.6.3. Using Synopsys* Design Constraint (SDC) on RTL Files 2.6.4. Post-Synthesis Static Timing Analysis (STA)
2.6.2. Running Synthesis x
2.6.2.1. Preserving Registers During Synthesis 2.6.2.2. Preserving Signals for Monitoring and Debugging 2.6.2.3. Viewing Synthesis Reports 2.6.2.4. Viewing Synthesis Dynamic Report
2.6.3. Using Synopsys* Design Constraint (SDC) on RTL Files x
2.6.3.1. Registering the SDC-on-RTL SDC File 2.6.3.2. Applying the SDC-on-RTL Constraints 2.6.3.3. Inspecting SDC-on-RTL Constraints 2.6.3.4. Creating Constraints in SDC-on-RTL SDC Files 2.6.3.5. Using Entity-Based SDC-on-RTL Constraints 2.6.3.6. Types of SDC Files Used in the Intel® Quartus® Prime Software 2.6.3.7. Example: Using SDC-on-RTL Features
2.7. Design Place and Route x
2.7.1. Running the Fitter 2.7.2. Viewing Fitter Reports
2.7.1. Running the Fitter x
2.7.1.1. Fitter Commands 2.7.1.2. Disabling or Enabling Physical Synthesis Optimization
2.7.2. Viewing Fitter Reports x
2.7.2.1. Plan Stage Reports 2.7.2.2. Place Stage Reports 2.7.2.3. Route Stage Reports 2.7.2.4. Retime Stage Reports 2.7.2.5. Finalize Stage Reports
2.7.2.2. Place Stage Reports x
2.7.2.2.1. Global Signal Visualization Report
2.7.2.3. Route Stage Reports x
2.7.2.3.1. Global Router Congestion Hotspot Summary Report 2.7.2.3.2. Global Router Wire Utilization Map Report
2.8. Incremental Optimization Flow x
2.8.1. Concurrent Analysis During Synthesis or Fitting 2.8.2. Analyzing Compiler Snapshots 2.8.3. Validating Periphery (I/O) after the Plan Stage
2.8.2. Analyzing Compiler Snapshots x
2.8.2.1. Running Snapshot Viewer
2.8.2.1. Running Snapshot Viewer x
2.8.2.1.1. Analyzing Failing Paths with Snapshot Viewer 2.8.2.1.2. Analyzing Clocking with Snapshot Viewer 2.8.2.1.3. Analyzing High Fan-out Nets with Snapshot Viewer 2.8.2.1.4. Validating Timing Constraints with Snapshot Viewer 2.8.2.1.5. Analyzing Congestion with Snapshot Viewer
2.9. Fast Forward Compilation Flow x
2.9.1. Step 1: Run Register Retiming 2.9.2. Step 2: Review Retiming Results 2.9.3. Step 3: Run Fast Forward Compile 2.9.4. Step 4: Review Fast Forward Results 2.9.5. Step 5: Implement Fast Forward Recommendations 2.9.6. Retiming Restrictions and Workarounds
2.9.2. Step 2: Review Retiming Results x
2.9.2.1. Locate Critical Chains
2.9.3. Step 3: Run Fast Forward Compile x
2.9.3.1. Fast Forward Compile By Hierarchy 2.9.3.2. HyperFlex Settings
2.9.4. Step 4: Review Fast Forward Results x
2.9.4.1. Clock Fmax Summary Report 2.9.4.2. Fast Forward Details Report
2.10. Full Compilation Flow x
2.10.1. Full Compilation Flow with Temporary Optimization Mode
2.12. Exporting Compilation Results x
2.12.1. Exporting a Version-Compatible Compilation Database 2.12.2. Importing a Version-Compatible Compilation Database 2.12.3. Creating a Design Partition 2.12.4. Exporting a Design Partition 2.12.5. Reusing a Design Partition 2.12.6. Viewing Quartus Database File Information 2.12.7. Clearing Compilation Results
2.12.6. Viewing Quartus Database File Information x
2.12.6.1. QDB File Attribute Types
2.13. Integrating Other EDA Tools x
2.13.1. Generating a VQM Netlist for other EDA Tools
2.14. Compiler Optimization Techniques x
2.14.1. Compiler Optimization Modes 2.14.2. Allow Register Retiming 2.14.3. Automatic Gated Clock Conversion 2.14.4. Enable Intermediate Fitter Snapshots 2.14.5. Fast Preserve Option 2.14.6. Fractal Synthesis Optimization
2.14.6. Fractal Synthesis Optimization x
2.14.6.1. Enabling or Disabling Fractal Synthesis
2.15. Synthesis Language Support x
2.15.1. Verilog and SystemVerilog Synthesis Support 2.15.2. VHDL Synthesis Support
2.15.1. Verilog and SystemVerilog Synthesis Support x
2.15.1.1. Verilog HDL Input Settings (Settings Dialog Box) 2.15.1.2. Design Libraries 2.15.1.3. Verilog HDL Configuration 2.15.1.4. Initial Constructs and Memory System Tasks 2.15.1.5. Verilog HDL Macros
2.15.1.3. Verilog HDL Configuration x
2.15.1.3.1. Hierarchical Design Configurations
2.15.2. VHDL Synthesis Support x
2.15.2.1. VHDL Input Settings (Settings Dialog Box) 2.15.2.2. VHDL Standard Libraries and Packages 2.15.2.3. VHDL wait Constructs 2.15.2.4. VHDL-2019 Conditional Analysis Tool Directives
2.16. Synthesis Settings Reference x
2.16.1. Advanced Synthesis Settings
3. Reducing Compilation Time x
3.1. Factors Affecting Compilation Results 3.2. Strategies to Reduce the Overall Compilation Time 3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time 3.4. Reducing Placement Time 3.5. Reducing Routing Time 3.6. Reducing Static Timing Analysis Time 3.7. Setting Process Priority 3.8. Reducing Compilation Time Revision History
3.2. Strategies to Reduce the Overall Compilation Time x
3.2.1. Running the ECO Compilation Flow 3.2.2. Enabling Multi-Processor Compilation 3.2.3. Using Block-Based Compilation
3.2.2. Enabling Multi-Processor Compilation x
3.2.2.1. Processor Base Clock Frequency 3.2.2.2. Random Access Memory (RAM) 3.2.2.3. Storage
3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time x
3.3.1. Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time 3.3.2. Use Appropriate Coding Style to Reduce Synthesis Time
3.4. Reducing Placement Time x
3.4.1. Placement Effort Multiplier Settings
3.5. Reducing Routing Time x
3.5.1. Identifying Routing Congestion with the Chip Planner
3.5.1. Identifying Routing Congestion with the Chip Planner x
3.5.1.1. Areas with Routing Congestion 3.5.1.2. Congestion due to HDL Coding style
1. Answers to Top FAQs
2. Design Compilation
3. Reducing Compilation Time
4. Intel® Quartus® Prime Pro Edition User Guide Design Compilation Archives
A. Intel® Quartus® Prime Pro Edition User Guides

2.11. Compilation Monitoring Mode

You can compile your design using the command-line interface (CLI) and the interactive Intel® Quartus® Prime Pro Edition GUI.
  • The CLI is generally helpful when your design is part of a larger script-based environment or the compilation is expected to take a significant amount of time. A log file is produced that you can examine at a later stage. However, it is difficult to examine and scroll through the textual output generated during a very long compilation. In such cases, use the Monitoring Mode.
  • The GUI presents the entire flow of a design along with tools and utilities for design, configuration, and debugging. The entire design is assumed to be contained in a single project directory.

Monitoring Mode

With the “Monitoring Mode,” you can bring up the Intel® Quartus® Prime Pro Edition GUI, connect to a project whose compilation has already been initiated on the CLI, and monitor the execution of the compilation in the GUI. It helps examine compilation-related messages in the interactive message window of the GUI, and in general, interact with the GUI in the same way as you would in the CLI. You can also view reports, view messages, and cross-probe to source files.

To use the Monitoring Mode, perform these steps:

  1. Start compiling your project through the CLI. For more information, refer to Compilation with quartus_sh --flow in the Intel® Quartus® Prime Pro Edition Scripting User Guide.
  2. Launch the Intel® Quartus® Prime Pro Edition GUI.
  3. Open the same project in the GUI that you are already compiling in the CLI. The Monitor Mode dialog appears, as shown in the following image:
    Figure 118. Monitoring Mode
  4. Select Open project and monitor the selected compiling revision and click OK. The Compilation Dashboard appears, displaying the status of the compilation, as shown in the following image:
    Note: Selecting Open project opens the project in the non-monitoring mode, but doing so might lead to design conflicts, where the underlying database might change unexpectedly and get corrupted. Selecting Don't open project cancels launching the project in the GUI.
    Figure 119. Monitoring the Compilation

    Once the compilation ends, the Monitoring Mode Ended message appears on the GUI, indicating you can continue in the GUI and perform other operations on your project.

Guidelines for Using the Monitoring Mode

Consider the following when using the monitoring mode:

  • You can start and exit the Intel® Quartus® Prime Pro Edition GUI in monitoring mode as often as you like without affecting the progress of the compilation underway.
  • If you are compiling multiple revisions of a project simultaneously, you can choose which revision compilation to monitor.
  • You cannot stop a monitored compilation in the GUI. You must stop it from the CLI.
  • After a monitored compilation finishes, the Intel® Quartus® Prime Pro Edition GUI automatically switches out of monitoring mode. However, if a new command-line compilation for the same project and revision starts, you are prompted to reenter the monitoring mode.
  • If you are currently compiling a project and revision from the CLI and open that design in the GUI without choosing the monitoring mode, you might cause design conflicts and corrupt the compilation database.
  • For a project being compiled, the project shown when the GUI is not in the monitoring mode might not reflect the most recent state of the project.
  • If you launch a new compilation of the project, the new compilation can corrupt the command-line compilation.
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