Cyclone® V Intel® FPGA IP for PCI Express* IP Core Release Notes

ID 683239
Date 7/31/2023
Public

1.4. Cyclone V Hard IP for PCI Express IP Core v15.0

Table 4.  v15.0 May 2015
Description Impact
In IP core variations with the Avalon-MM DMA interface, added support for downstream burst read request for a payload of size up to 4 KBytes, if Enable burst capability for RXM BAR2 port is turned on in the Parameter Editor. Previous maximum downstream read request payload size was 512 bytes. If you choose the Avalon-MM DMA interface, the IP core can receive and process a burst read request for a payload of any size supported by the PCI Express specification (up to 4 KBytes), if it receives such a burst read request on the PCI Express link.
In IP core variations with the Avalon-MM interface, added support to send message TLPs with data payload of any length from a Root Port. If you choose the Avalon-MM interface, a Root Port IP core can send messages with payload greater than 1 dword.