AN 370: Using the Intel FPGA Serial Flash Loader with the Intel Quartus Prime Software

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ID 683299
Date 2/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software
1. Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software x
1.1. Features 1.2. Overview 1.3. Programming Single and Multiple Serial Configuration Devices with the Intel® FPGA Serial Flash Loader IP Core 1.4. Using the Intel® FPGA Serial Flash Loader IP Core in the Intel® Quartus® Prime Software 1.5. Generating .jic and .jam Programming Files in the Intel® Quartus® Prime Software 1.6. Programming Serial Configuration Devices with the Intel® Quartus® Prime Programmer 1.7. Features for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 1.8. Intel® FPGA Serial Flash Loader IP Core Parameter 1.9. Intel® FPGA Serial Flash Loader IP Core Signals 1.10. Document Revision History for AN 370: Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software
1.4. Using the Intel® FPGA Serial Flash Loader IP Core in the Intel® Quartus® Prime Software x
1.4.1. Instantiating the Intel® FPGA Serial Flash Loader IP Core
1.5. Generating .jic and .jam Programming Files in the Intel® Quartus® Prime Software x
1.5.1. Converting .sof to .jic Files in the Intel® Quartus® Prime Software 1.5.2. Converting .jic Files to .jam Files in the Intel® Quartus® Prime Software
1.6. Programming Serial Configuration Devices with the Intel® Quartus® Prime Programmer x
1.6.1. Programming Serial Configuration Devices Using the Intel® Quartus® Prime Programmer and .jic Files 1.6.2. Programming Serial Configuration Devices Using the Intel® Quartus® Prime Programmer and .jam Files
1.7. Features for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
1.7.1. Multiple Configuration Devices Support 1.7.2. Boot Page Selection
1. Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software

1.6.1. Programming Serial Configuration Devices Using the Intel® Quartus® Prime Programmer and .jic Files

To program serial configuration devices with .jic files, you must perform the following steps:
  1. When the .sof-to-.jic file conversion is complete, add the .jic file to the Intel® Quartus® Prime programmer window:
    1. In the Tools menu, choose Programmer. The Chain1.cdf dialog box appears.
    2. Click Add File. In the Select Programming File dialog box, browse to the .jic file.
    3. Click Open.
  2. Configure the FPGA with the SFL image by turning on the FPGA Program/Configure box. This process corresponds to Step 1. After the Program/Configure box is turned on, the Intel® Quartus® Prime programmer automatically invokes the factory default enhanced SFL image.
    Note: The Check block CRCs or perform on-chip verification to accelerate PFL/SFL verification when available check box under Tools > Options > Programmer tab is another relevant option for the enhanced mode SFL solution. This check box is turned on by default to speed up the EPCS image verification process using CRC method. The verification takes place when you turn on the Verify check box in the Intel® Quartus® Prime programmer. If you do not use this option, turn off the check box.
  3. Program the serial configuration device by turning on the corresponding Program/Configure box, and then click Start. This process corresponds to Step 2.
Note: If the Program/Configure check boxes are not specified, the Intel® Quartus® Prime programmer bypasses the request. Also, if the FPGA does not have the SFL image when the serial configuration device data is programmed through the JTAG interface, the programming process fails.

You can program multiple serial configuration devices by including more than one .jic file in the Intel® Quartus® Prime programmer.

Note: Your FPGA must be in active serial configuration mode to enable the Intel® FPGA Serial Flash Loader IP core to program.
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