Low Latency 100G Ethernet Design Example User Guide

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ID 683371
Date 11/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. LL 100GbE Design Example Description A. Document Revision History
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design Example in Hardware
2. LL 100GbE Design Example Description x
2.1. Features 2.2. Software and Hardware Requirements 2.3. Functional Description 2.4. Design Variations 2.5. Interface Signals 2.6. Design Example Registers
2.4. Design Variations x
2.4.1. Standard CAUI IP Core Variation 2.4.2. CAUI-4 IP Core Variation
1. Quick Start Guide
2. LL 100GbE Design Example Description
A. Document Revision History

1.4. Simulating the Design

Figure 6. Procedure
Table 1.   LL 100GbE IP Core Testbench File DescriptionsLists the key files that implement the example testbenches.

File Names

Description

Testbench and Simulation Files

basic_avl_tb_top.v Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.

Testbench Scripts

run_vsim.do

The ModelSim script to run the testbench.

run_vcs.sh

The Synopsys VCS script to run the testbench.

run_ncsim.sh

The Cadence NCSim script to run the testbench.

Follow these steps to simulate the testbench:

  1. Change to the testbench simulation directory <design_example_dir>/example_testbench.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table "Steps to Simulate the Testbench".
  3. Analyze the results. The successful testbench sends ten packets, receives ten packets, and displays "Testbench complete."
    Table 2.  Steps to Simulate the Testbench
    Simulator Instructions
    ModelSim In the command line, type vsim -do run_vsim.do

    If you prefer to simulate without bringing up the ModelSim GUI, type vsim -c -do run_vsim.do

    Note: The ModelSim® - Intel FPGA Edition simulator does not have the capacity to simulate this IP core. You must use another supported ModelSim simulator such as ModelSim SE.
    NCSim In the command line, type sh run_ncsim.sh
    VCS In the command line, type sh run_vcs.sh
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