AN-785: Altera JESD204B IP Core and ADI AD9162 Hardware Checkout Report

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ID 683452
Date 12/06/2016
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B IP Core and AD9162 Hardware Checkout Report
1. JESD204B IP Core and AD9162 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and DAC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer 1.3.2. Transceiver Transport Layer 1.3.3. Scrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Transmitter Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B IP Core and AD9162 Hardware Checkout Report

1.6. Test Result Comments

In each test case, the TX JESD204B IP core successfully initializes from CGS phase, ILA phase, and until user data phase. The behavior of the TX JESD204B IP core meets the passing criteria.

No data integrity issue is observed from the short transport layer (STPL) test pattern checkers at DAC JESD core for all modes except with 3 and 6 lanes. In these modes, the DAC does not support the STPL test. Sine wave at transmitted frequency is observed at analog channel when sine wave generators in FPGA are enabled for all supported JESD modes.

In the deterministic latency measurement, consistent total latency is observed across the JESD204B link and DAC analog channels.

Level Two Title