Intel® FPGA Programmable Acceleration Card D5005 Data Sheet

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ID 683568
Date 11/04/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Board Management Controller 4. FPGA Interface Manager 5. System Compatibility 6. Power Requirements 7. Mechanical Information 8. Thermal and Airflow Requirements A. Safety and Regulatory Information B. Revision History
2. Overview x
2.1. Intel® FPGA PAC D5005 Specifications 2.2. Intel® FPGA PAC Components
2.2. Intel® FPGA PAC Components x
2.2.1. Intel® Stratix® 10 FPGA 2.2.2. Power 2.2.3. PCIe* Interface 2.2.4. DDR4 SDRAM 2.2.5. Network Interface 2.2.6. Field Replaceable Unit Identification EEPROM 2.2.7. MAC Address EEPROM 2.2.8. Flash Memory 2.2.9. Control and Support
3. Board Management Controller x
Features of the BMC 3.1. Health Monitoring Features 3.2. Supported PLDM/MCTP Commands
7. Mechanical Information x
7.1. Ports and LEDs
8. Thermal and Airflow Requirements x
8.1. Thermal Cooling Requirements 8.2. Airflow Requirements
A. Safety and Regulatory Information x
A.1. Regulatory Compliance
1. Introduction
2. Overview
3. Board Management Controller
4. FPGA Interface Manager
5. System Compatibility
6. Power Requirements
7. Mechanical Information
8. Thermal and Airflow Requirements
A. Safety and Regulatory Information
B. Revision History

3. Board Management Controller

A Board Management Controller (BMC) resides on the Intel® FPGA PAC. The BMC is responsible for controlling, monitoring and granting access to board features. The Intel® MAX® 10 BMC interfaces with on-board sensors, the FPGA and the flash, and it controls power-on/power-off sequences, FPGA configuration and telemetry data polling. The BMC communicates using the Platform Level Data Model (PLDM) version 1.1.1 protocol. The BMC firmware is field upgradeable over PCIe* using the remote system update feature.

Features of the BMC

  • Interfaces with sensors, FPGA, flash and QSFPs
  • FPGA configuration and reconfiguration
  • Controls BMC firmware and Intel® Stratix® 10 FPGA flash updates. Updates are provided over PCIe.
  • Monitors telemetry data (board temperature, voltage and current) and provides protective action when readings are outside of critical threshold
  • Reports telemetry data to host BMC via Platform Level Data Model (PLDM) over MCTP SMBus or Standard I2C
  • Supports PLDM over MCTP SMBus via PCIe* SMBus. 0xCE is a 8-bit slave address. Raw 7-bit slave address is 0x67
  • Supports Standard I2C via PCIe* SMBus. The I2C slave address is 0xBC (8-bit)
  • Intel® FPGA Download Cable functionality for the board
  • Power up / down sequencing and fault detection with automatic shut-down protection
  • Controls programmable FPGA and DDR4 SDRAM clocks for performance throttling if desired
  • Controls power and resets on the board
  • Acts as a Root of Trust (RoT) and enables the secure update features of the Intel® FPGA PAC D5005. The RoT includes features that may help prevent the following:
    • Loading or executing of unauthorized code or designs.
    • Disruptive operations attempted by unprivileged software, privileged software, or the host BMC.
    • Unintended execution of older code or designs with known bugs or vulnerabilities by enabling the BMC to revoke authorization.
  • Enforces several other security policies relating to access through various interfaces, as well as protecting the on-board flash through write rate limitation.

Refer to the Intel® FPGA PAC D5005 Board Management Controller User Guide for more information.

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