AN 706: Routing HPS Peripheral Signals to the FPGA External Interface

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ID 683659
Date 5/07/2018
Public
Document Table of Contents
Document Table of Contents x
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface x
1.1. Cyclone® V and Arria® V HPS Peripherals That Support Routing to the FPGA 1.2. Design Example: Cyclone® V HPS IP Interface to FPGA 1.3. Sample Application Example 1.4. Reference Documents 1.5. AN 706 Revision History
1.2. Design Example: Cyclone® V HPS IP Interface to FPGA x
1.2.1. Prerequisites 1.2.2. Getting Started 1.2.3. Generating the Initial HDL in Platform Designer (Standard) 1.2.4. Top Level Routing 1.2.5. Timing Constraint Configuration 1.2.6. Adding Pin Assignments in Intel® Quartus® Prime Standard Edition 1.2.7. Hardware Programming File Compilation and Generation 1.2.8. SD Card Image Updates 1.2.9. Board Setup and Booting Linux from the SD Card
1.2.1. Prerequisites x
1.2.1.1. Hardware Requirements 1.2.1.2. Software Requirements
1.2.8. SD Card Image Updates x
1.2.8.1. Preloader Generation 1.2.8.2. U-boot Setup 1.2.8.3. Device Tree Setup
1.3. Sample Application Example x
1.3.1. EMAC Test 1.3.2. I2C Test
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface

1.2.8.3. Device Tree Setup

Generate the device tree. EMAC0 is enabled in the device tree source, as shown below, and the I2C0 code source maintains its default settings. 


aliases   {   
                  ethernet0 = "/soc/ethernet@ff700000";
          }; 
ethernet@ff700000 {
                     compatible = "altr,socfpga-stmmac","snps,dwmac-3.70a", "snps,dwmac";
                     reg = <0xff700000 0x2000>;
                     interrupts = <0x0 0x73 0x4>;
                     interrupt-names = "macirq";
                     mac-address = [00 00 00 00 00 00];
                     clocks = <0xd>;
                     clock-names = "stmmaceth";
                     status = "okay";
                     phy-mode = "mii";
                     phy-add r= <0xffffffff>;
                     snsp,
                  };
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