Stratix V Device Handbook: Volume 2: Transceivers

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ID 683779
Date 11/23/2021
Public
Document Table of Contents
Document Table of Contents x
1. Transceiver Architecture in Stratix V Devices 2. Transceiver Clocking in Stratix V Devices 3. Transceiver Reset Control in Stratix V Devices 4. Transceiver Configurations in Stratix V Devices 5. Transceiver Loopback Support in Stratix V Devices 6. Dynamic Reconfiguration in Stratix V Devices
1. Transceiver Architecture in Stratix V Devices x
1.1. Device Layout 1.2. PMA Architecture 1.3. Standard PCS Architecture 1.4. 10G PCS Architecture 1.5. PCIe Gen3 PCS Architecture 1.6. Document Revision History
1.1. Device Layout x
1.1.1. Stratix V GX/GT Channel and PCIe Hard IP Layout 1.1.2. Stratix V GS Channel and PCIe Hard IP Layout
1.1.2. Stratix V GS Channel and PCIe Hard IP Layout x
1.1.2.1. Channel Variants 1.1.2.2. GS/GT/GX Device Variants and Packages
1.2. PMA Architecture x
1.2.1. Receiver Buffer 1.2.2. Receiver Clock Data Recovery Unit 1.2.3. Receiver Deserializer 1.2.4. Transmitter PLLs 1.2.5. Transmitter Serializer 1.2.6. Transmitter Buffer 1.2.7. Transceiver Calibration Blocks 1.2.8. PMA Reconfiguration
1.2.1. Receiver Buffer x
1.2.1.1. Receiver Equalizer Gain Bandwidth 1.2.1.2. Programmable Differential On-Chip Termination (OCT) 1.2.1.3. Programmable VCM 1.2.1.4. Signal Threshold Detection Circuitry 1.2.1.5. DC Gain 1.2.1.6. Continuous Time Linear Equalization (CTLE) 1.2.1.7. Decision Feedback Equalization 1.2.1.8. EyeQ
1.2.1.8. EyeQ x
1.2.1.8.1. Serial Bit Checker
1.2.2. Receiver Clock Data Recovery Unit x
1.2.2.1. Lock-to-Reference Mode 1.2.2.2. Lock-to-Data Mode 1.2.2.3. CDR Lock Modes
1.2.2.3. CDR Lock Modes x
1.2.2.3.1. Automatic Lock Mode 1.2.2.3.2. Manual Lock Mode
1.2.3. Receiver Deserializer x
1.2.3.1. Receiver PMA Bit-Slip
1.2.4. Transmitter PLLs x
1.2.4.1. Channel PLL Used as a CMU PLL (Transmitter PLL) 1.2.4.2. Auxiliary Transmit (ATX) PLL Architecture
1.2.6. Transmitter Buffer x
1.2.6.1. Transmitter Analog Settings 1.2.6.2. Programmable Transmitter On-Chip Termination (OCT) 1.2.6.3. Link Coupling
1.2.7. Transceiver Calibration Blocks x
1.2.7.1. OCT Calibration 1.2.7.2. Offset Cancellation in the Receiver Buffer and Receiver CDR 1.2.7.3. ATX PLL Calibration 1.2.7.4. Calibration Block Boundary
1.3. Standard PCS Architecture x
1.3.1. Receiver Standard PCS Datapath 1.3.2. Transmitter Standard PCS Datapath
1.3.1. Receiver Standard PCS Datapath x
1.3.1.1. Word Aligner 1.3.1.2. PRBS Verifier 1.3.1.3. Deskew FIFO 1.3.1.4. Rate Match (Clock Rate Compensation) FIFO 1.3.1.5. 8B/10B Decoder 1.3.1.6. Byte Deserializer 1.3.1.7. Byte Ordering Block 1.3.1.8. Receiver Phase Compensation FIFO
1.3.1.8. Receiver Phase Compensation FIFO x
1.3.1.8.1. Phase Compensation Mode 1.3.1.8.2. Registered Mode
1.3.2. Transmitter Standard PCS Datapath x
1.3.2.1. Transmitter Phase Compensation FIFO 1.3.2.2. Byte Serializer 1.3.2.3. 8B/10B Encoder Control Code Encoding Reset Condition Transmitter Polarity Inversion Transmitter Bit-Slip 1.3.2.4. PRBS Generator
1.4. 10G PCS Architecture x
1.4.1. Receiver 10G PCS Datapath 1.4.2. Transmitter 10G PCS Datapath
1.4.1. Receiver 10G PCS Datapath x
1.4.1.1. Receiver Gearbox 1.4.1.2. PRBS Verifier 1.4.1.3. Block Synchronizer 1.4.1.4. Disparity Checker 1.4.1.5. Descrambler 1.4.1.6. Frame Synchronizer 1.4.1.7. Bit-Error Rate (BER) Monitor 1.4.1.8. PRP Verifier 1.4.1.9. 64B/66B Decoder 1.4.1.10. CRC-32 Checker 1.4.1.11. Receiver FIFO
1.4.1.2. PRBS Verifier x
1.4.1.2.1. Receiver Inversion
1.4.2. Transmitter 10G PCS Datapath x
1.4.2.1. Transmitter FIFO 1.4.2.2. Frame Generator 1.4.2.3. CRC-32 Generator 1.4.2.4. 64B/66B Encoder 1.4.2.5. Scrambler 1.4.2.6. Disparity Generator 1.4.2.7. PRBS Generator 1.4.2.8. Transmitter Gearbox
1.4.2.5. Scrambler x
1.4.2.5.1. PRP Generator
1.4.2.7. PRBS Generator x
1.4.2.7.1. Transmitter Inversion
1.5. PCIe Gen3 PCS Architecture x
1.5.1. Receiver PCIe Gen3 PCS Datapath 1.5.2. Transmitter PCIe Gen3 PCS Datapath 1.5.3. PIPE Interface
1.5.1. Receiver PCIe Gen3 PCS Datapath x
1.5.1.1. Block Synchronizer 1.5.1.2. Rate Match FIFO 1.5.1.3. Decoder 1.5.1.4. Descrambler 1.5.1.5. Receiver Phase Compensation FIFO
1.5.2. Transmitter PCIe Gen3 PCS Datapath x
1.5.2.1. Transmitter Phase Compensation FIFO 1.5.2.2. Scrambler 1.5.2.3. Encoder 1.5.2.4. Gearbox
1.5.3. PIPE Interface x
1.5.3.1. Auto Speed Negotiation 1.5.3.2. Electrical Idle Inference 1.5.3.3. Clock Data Recovery (CDR) Control
2. Transceiver Clocking in Stratix V Devices x
2.1. Input Reference Clocking 2.2. Internal Clocking 2.3. FPGA Fabric-Transceiver Interface Clocking 2.4. Document Revision History
2.1. Input Reference Clocking x
2.1.1. Input Reference Clock Sources
2.1.1. Input Reference Clock Sources x
2.1.1.1. Dedicated refclk Pins 2.1.1.2. Dedicated refclk Pins Using the Reference Clock Network 2.1.1.3. RX Pins Using the Reference Clock Network 2.1.1.4. Fractional PLLs
2.2. Internal Clocking x
2.2.1. Transmitter Clock Network 2.2.2. Transmitter Clocking 2.2.3. Receiver Clocking
2.2.1. Transmitter Clock Network x
2.2.1.1. Transmitter Clock Lines 2.2.1.2. Clock Dividers 2.2.1.3. Transmitter Clock Network in Stratix V GT Transceiver Channels
2.2.2. Transmitter Clocking x
2.2.2.1. Transmitter 10G PCS Clocking 2.2.2.2. Transmitter Standard PCS Clocking 2.2.2.3. Transmitter GT Channel Clocking
2.2.2.2. Transmitter Standard PCS Clocking x
2.2.2.2.1. Non-Bonded Channel Configurations Using the x1 Clock Network 2.2.2.2.2. Non-Bonded Channel Configurations Using the xN Clock Network 2.2.2.2.3. Bonded Channel Configurations 2.2.2.2.4. Bonded Channel Configurations Using the xN Clock Network 2.2.2.2.5. Bonded Channel Configurations Using the PLL Feedback Compensation Path
2.2.3. Receiver Clocking x
2.2.3.1. GX Channel Receiver Clocking 2.2.3.2. GT Channel Receiver Clocking
2.2.3.1. GX Channel Receiver Clocking x
2.2.3.1.1. Non-Bonded Channel Configurations 2.2.3.1.2. Bonded Channel Configurations
2.3. FPGA Fabric-Transceiver Interface Clocking x
2.3.1. Transmitter Datapath Interface Clocking 2.3.2. Receiver Datapath Interface Clock 2.3.3. GXB 0 PPM Core Clock Assignment
2.3.1. Transmitter Datapath Interface Clocking x
2.3.1.1. Quartus II-Selected Transmitter Datapath Interface Clock 2.3.1.2. Selecting a Transmitter Datapath Interface Clock
2.3.2. Receiver Datapath Interface Clock x
2.3.2.1. Quartus II Software-Selected Receiver Datapath Interface Clock 2.3.2.2. Selecting a Receiver Datapath Interface Clock
3. Transceiver Reset Control in Stratix V Devices x
3.1. PHY IP Embedded Reset Controller 3.2. User-Coded Reset Controller 3.3. Transceiver Reset Using Avalon Memory Map Registers 3.4. Clock Data Recovery in Manual Lock Mode 3.5. Transceiver Blocks Affected by the Reset and Powerdown Signals 3.6. Document Revision History
3.1. PHY IP Embedded Reset Controller x
3.1.1. Embedded Reset Controller Signals 3.1.2. Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device Power-Up 3.1.3. Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device Operation
3.2. User-Coded Reset Controller x
3.2.1. User-Coded Reset Controller Signals 3.2.2. Resetting the Transmitter with the User-Coded Reset Controller During Device Power-Up 3.2.3. Resetting the Transmitter with the User-Coded Reset Controller During Device Operation 3.2.4. Resetting the Receiver with the User-Coded Reset Controller During Device Power-Up Configuration 3.2.5. Resetting the Receiver with the User-Coded Reset Controller During Device Operation
3.3. Transceiver Reset Using Avalon Memory Map Registers x
3.3.1. Transceiver Reset Control Signals Using Avalon Memory Map Registers
3.4. Clock Data Recovery in Manual Lock Mode x
3.4.1. Control Settings for CDR Manual Lock Mode 3.4.2. Resetting the Transceiver in CDR Manual Lock Mode
4. Transceiver Configurations in Stratix V Devices x
4.1. Protocols and Transceiver PHY IP Support 4.2. 10GBASE-R and 10GBASE-KR 4.3. Interlaken 4.4. PCI Express (PCIe)—Gen1, Gen2, and Gen3 4.5. XAUI 4.6. CPRI and OBSAI—Deterministic Latency Protocols 4.7. Transceiver Configurations 4.8. Native PHY IP Configuration 4.9. Stratix V GT Device Configurations 4.10. Document Revision History
4.2. 10GBASE-R and 10GBASE-KR x
4.2.1. 10GBASE-R and 10GBASE-KR Transceiver Datapath Configuration 4.2.2. 10GBASE-R and 10GBASE-KR Supported Features 4.2.3. 1000BASE-X and 1000BASE-KX Transceiver Datapath 4.2.4. 1000BASE-X and 1000BASE-KX Supported Features 4.2.5. Synchronization State Machine Parameters in 1000BASE-X and 1000BASE-KX Configurations 4.2.6. Transceiver Clocking in 10GBASE-R, 10GBASE-KR, 1000BASE-X, and 1000BASE-KX Configurations
4.3. Interlaken x
4.3.1. Transceiver Datapath Configuration 4.3.2. Supported Features 4.3.3. Transceiver Clocking
4.4. PCI Express (PCIe)—Gen1, Gen2, and Gen3 x
4.4.1. Transceiver Datapath Configuration 4.4.2. Supported Features for PCIe Configurations 4.4.3. Supported Features for PCIe Gen3 4.4.4. Transceiver Clocking and Channel Placement Guidelines 4.4.5. Advanced Channel Placement Guidelines for PIPE Configurations 4.4.6. Transceiver Clocking for PCIe Gen3
4.5. XAUI x
4.5.1. Transceiver Datapath in a XAUI Configuration 4.5.2. Supported Features 4.5.3. Transceiver Clocking and Channel Placement Guidelines
4.6. CPRI and OBSAI—Deterministic Latency Protocols x
4.6.1. Transceiver Datapath Configuration 4.6.2. Phase Compensation FIFO in Register Mode 4.6.3. Channel PLL Feedback 4.6.4. CPRI and OBSAI 4.6.5. CPRI Enhancements
4.7. Transceiver Configurations x
4.7.1. Standard PCS Configurations—Custom Datapath 4.7.2. Standard PCS Configurations—Low Latency Datapath 4.7.3. Transceiver Channel Placement Guidelines 4.7.4. 10G PCS Configurations 4.7.5. Merging Instances
4.7.4. 10G PCS Configurations x
4.7.4.1. 10G PCS Datapath Functionality 4.7.4.2. Using the coreclkin Ports
4.8. Native PHY IP Configuration x
4.8.1. Native PHY Transceiver Datapath Configuration 4.8.2. Standard PCS Features 4.8.3. 10G PCS Supported Features 4.8.4. 10G Datapath Configurations with Native PHY IP 4.8.5. PMA Direct Supported Features 4.8.6. Channel and PCS Datapath Dynamic Switching Reconfiguration
4.8.2. Standard PCS Features x
4.8.2.1. Standard PCS Receiver and Transmitter Blocks
4.8.3. 10G PCS Supported Features x
4.8.3.1. 10G PCS Receiver and Transmitter Blocks 4.8.3.2. Receiver and Transmit Gearbox in Native PHY IP
5. Transceiver Loopback Support in Stratix V Devices x
5.1. Serial Loopback 5.2. PIPE Reverse Parallel Loopback 5.3. Reverse Serial Loopback 5.4. Reverse Serial Pre-CDR Loopback 5.5. Document Revision History
6. Dynamic Reconfiguration in Stratix V Devices x
6.1. Dynamic Reconfiguration Features 6.2. Offset Cancellation 6.3. PMA Analog Controls Reconfiguration 6.4. On-Chip Signal Quality Monitoring (Eye Viewer) 6.5. Decision Feedback Equalization 6.6. Adaptive Equalization 6.7. Dynamic Reconfiguration of Loopback Modes 6.8. Transceiver PLL Reconfiguration 6.9. Transceiver Channel Reconfiguration 6.10. Transceiver Interface Reconfiguration 6.11. Document Revision History
1. Transceiver Architecture in Stratix V Devices
2. Transceiver Clocking in Stratix V Devices
3. Transceiver Reset Control in Stratix V Devices
4. Transceiver Configurations in Stratix V Devices
5. Transceiver Loopback Support in Stratix V Devices
6. Dynamic Reconfiguration in Stratix V Devices

1.3.2.3. 8B/10B Encoder

The 8B/10B encoder generates 10-bit code groups from the 8-bit data and 1-bit control identifier. In 8-bit width mode, the 8B/10B encoder translates the 8-bit data to a 10-bit code group (control word or data word) with proper disparity. If the tx_datak input is high, the 8B/10B encoder translates the input data[7:0] to a 10-bit control word. If the tx_datak input is low, the 8B/10B encoder translates the input dat a[7:0] to a 10-bit data word.

Figure 30. 8B/10B Conversion Format

Control Code Encoding

The IEEE 802.3 8B/10B encoder specification identifies only a set of 8-bit characters for which tx_datak must be asserted. If you assert tx_datak for any other set of bytes, the 8B/10B encoder might encode the output 10-bit code as an invalid code (it does not map to a valid Dx.y or Kx.y code), or unintended valid Dx.y code, depending on the value entered. It is possible for a downstream 8B/10B decoder to decode an invalid control word into a valid Dx.y code without asserting code error flags.

Figure 31. Control Word and Data Word Transmission

Reset Condition

The tx_digitalreset signal resets the 8B/10B encoder. During reset, running disparity (RD) and data registers are cleared. Also, the 8B/10B encoder outputs a K28.5 pattern from the RD- column continuously until tx_digitalreset is deasserted. The input data and control code from the FPGA fabric is ignored during the reset state. After reset, the 8B/10B encoder starts with an RD being negative (RD-) and transmits three K28.5 code groups for synchronization before it starts encoding and transmitting the data on its output.

Note: While tx_digitalreset is asserted, the downstream 8B/10B decoder that receives the data may observe synchronization or disparity errors.

When in reset (tx_digitalreset is high), a K28.5- (K28.5 10-bit code group from the RD-column) is sent continuously until tx_digitalreset is low. Because of some pipelining of the transmitter channel PCS, some “don’t cares” (10’hxxx) are sent before the three synchronizing K28.5 code groups. User data follows the third K28.5 code group.

Figure 32. 8B/10B Encoder Output During tx_digitalreset Deassertion

Transmitter Polarity Inversion

The positive and negative signals of a serial differential link may be erroneously swapped during board layout. Solutions such as board re-spin or major updates to the PLD logic are expensive. The transmitter polarity inversion feature of the 8B/10B encoder is provided to correct this situation.

Transmitter Bit-Slip

The transmitter bit-slip allows you to compensate for the channel-to-channel skew between multiple transmitter channels by slipping the data sent to the physical medium attachment (PMA).

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