Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

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ID 683814
Date 1/14/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines x
Intel® Arria® 10 GX and GT Pin Connection Guidelines Intel® Arria® 10 SX Pin Connection Guidelines Power Supply Sharing Guidelines for Intel® Arria® 10 Devices Document Revision History for the Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
Intel® Arria® 10 GX and GT Pin Connection Guidelines x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins Partial Reconfiguration Pins 3V Compatible I/O Pins Differential I/O Pins External Memory Interface and Hard Memory PHY Pins Reference Pins Voltage Sensor Pins Supply Pins Transceiver Pins Notes to Intel® Arria® 10 GX and GT Pin Connection Guidelines
Intel® Arria® 10 SX Pin Connection Guidelines x
HPS Supply Pins HPS Dedicated I/O Bank Pins HPS Peripheral Pins Shared 3V I/O Bank Pins Notes to Intel® Arria® 10 SX Pin Connection Guidelines
Power Supply Sharing Guidelines for Intel® Arria® 10 Devices x
Example 1— Intel® Arria® 10 GX Example 2— Intel® Arria® 10 GX Example 3— Intel® Arria® 10 GX Example 4— Intel® Arria® 10 GT Example 5— Intel® Arria® 10 GT Example 6— Intel® Arria® 10 GT Example 7— Intel® Arria® 10 GT Example 8— Intel® Arria® 10 SX Example 9— Intel® Arria® 10 SX Example 10— Intel® Arria® 10 SX Example 11— Intel® Arria® 10 GX (Using the SmartVID Feature) Notes to Power Supply Sharing Guidelines
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

Reference Pins

Note: Intel® recommends that you create a Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 8.  Reference Pins
Pin Name Pin Functions Pin Description Connection Guidelines
RZQ_[#] , VID_EN I/O Reference pins for I/O banks. The RZQ pins share the same VCCIO with the I/O bank where they are located. Connect the external precision resistor to the designated pin within the bank. If not required, this pin is a regular I/O pin.

When using OCT tie these pins to GND through either a 240-Ω or 100-Ω resistor, depending on the desired OCT impedence. Refer to the Intel® Arria® 10 Device Handbook for the OCT impedence options for the desired OCT scheme.

If you are using the Early I/O Release feature in the Intel® Arria® 10 SX devices, ensure that this pin is located within the active HPS I/O banks. For more information, refer to the HPS EMIF Design Consideration chapter of the Intel® Arria® 10 SoC Design Guidelines.

The VID_EN pin is not a physical pin. The VID_EN pin is a multi-function shared pin with the RZQ_2A pin.

If you are using the SmartVID feature, you have the option to enable the VID_EN function using the RZQ_2A pin. If you use the RZQ_2A pin as the VID_EN pin, you cannot use the RZQ_2A pin for OCT calibration.

If you are using the RZQ_2A pin for OCT calibration, you have the option to use other available general-purpose I/O pins for the VID_EN function.

DNU Do Not Use Do Not Use (DNU). Do not connect to power, GND, or any other signal. These pins must be left floating.
NC No Connect Do not drive signals into these pins.

When designing for device migration, you have the option to connect these pins to either power, GND, or a signal trace depending on the pin assignment of the devices selected for migration.

However, if device migration is not a concern, leave these pins floating.
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