External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Public
Document Table of Contents

5.9. Document Revision History

Date Version Changes
March 2023 2023.03.06 Removed Intel® Arria® 10 and Intel® Stratix® 10 references.
May 2017 2017.5.08
  • Added Stratix 10 to RLDRAM II and RLDRAM 3 Layout Guidelines section.
  • Rebranded as Intel.
October 2016 2016.10.31 Maintenance release.
May 2016 2016.05.02 Maintenance release.
November 2015 2015.11.02
  • Changed instances of Quartus II to Quartus Prime.
May 2015 2015.05.04 Maintenance release.
December 2014 2014.12.15 Maintenance release.
August 2014 2014.08.15
  • Revised RLDRAM 3 Termination Recommendations for Arria V GZ and Stratix V Devices table.
  • Removed millimeter approximations from lengths expressed in picoseconds in RLDRAM II and RLDRAM 3 Layout Guidelines table.
  • Minor formatting fixes in RLDRAM II and RLDRAM 3 Layout Guidelines table.
  • Added Layout Approach section.
December 2013 2013.12.16
  • Added note about byteenable support to Signal Descriptions section.
  • Consolidated General Layout Guidelines.
November 2012 3.2 Added content supporting RLDRAM 3 and updated RLDRAM II standards.
June 2012 3.1 Added Feedback icon.
November 2011 3.0 Added Arria V information.
June 2011 2.0 Added Stratix V information.
December 2010 1.0 Initial release.