External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

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ID 683385
Date 3/06/2023
Public
Document Table of Contents
Document Table of Contents x
1. Planning Pin and FPGA Resources 2. DDR2 and DDR3 SDRAM Board Design Guidelines 3. Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines 4. LPDDR2 SDRAM Board Design Guidelines 5. RLDRAM II and RLDRAM 3 Board Design Guidelines 6. QDR II/II+ SRAM Board Design Guidelines 7. Implementing and Parameterizing Memory IP 8. Simulating Memory IP 9. Analyzing Timing of Memory IP 10. Debugging Memory IP 11. Optimizing the Controller 12. PHY Considerations 13. Power Estimation Methods for External Memory Interfaces
1. Planning Pin and FPGA Resources x
1.1. Interface Pins 1.2. Guidelines for UniPHY-based External Memory Interface IP 1.3. Using PLL Guidelines 1.4. PLL Cascading 1.5. DLL 1.6. Other FPGA Resources 1.7. Document Revision History
1.1. Interface Pins x
1.1.1. Estimating Pin Requirements 1.1.2. DDR, DDR2, and DDR3 SDRAM Clock Signals 1.1.3. DDR, DDR2, and DDR3 SDRAM Command and Address Signals 1.1.4. DDR, DDR2, and DDR3 SDRAM Data, Data Strobes, DM/DBI, and Optional ECC Signals 1.1.5. DDR, DDR2, and DDR3 SDRAM DIMM Options 1.1.6. QDR II and QDR II+ SRAM Clock Signals 1.1.7. QDR II and QDR II+ SRAM Command Signals 1.1.8. QDR II and QDR II+ SRAM Address Signals 1.1.9. QDR II and QDR II+ SRAM Data, BWS, and QVLD Signals 1.1.10. RLDRAM II and RLDRAM 3 Clock Signals 1.1.11. RLDRAM II and RLDRAM 3 Commands and Addresses 1.1.12. RLDRAM II and RLDRAM 3 Data, DM and QVLD Signals 1.1.13. LPDDR2 Clock Signal 1.1.14. LPDDR2 Command and Address Signal 1.1.15. LPDDR2 Data, Data Strobe, and DM Signals 1.1.16. Maximum Number of Interfaces 1.1.17. OCT Support
1.1.16. Maximum Number of Interfaces x
1.1.16.1. Maximum Number of DDR SDRAM Interfaces Supported per FPGA 1.1.16.2. Maximum Number of DDR2 SDRAM Interfaces Supported per FPGA 1.1.16.3. Maximum Number of DDR3 SDRAM Interfaces Supported per FPGA 1.1.16.4. Maximum Number of QDR II and QDR II+ SRAM Interfaces Supported per FPGA 1.1.16.5. Maximum Number of RLDRAM II Interfaces Supported per FPGA 1.1.16.6. Maximum Number of LPDDR2 SDRAM Interfaces Supported per FPGA
1.2. Guidelines for UniPHY-based External Memory Interface IP x
1.2.1. General Pin-out Guidelines for UniPHY-based External Memory Interface IP 1.2.2. Pin-out Rule Exceptions for ×36 Emulated QDR II and QDR II+ SRAM Interfaces in Arria II, Stratix III and Stratix IV Devices 1.2.3. Pin-out Rule Exceptions for RLDRAM II and RLDRAM 3 Interfaces 1.2.4. Pin-out Rule Exceptions for QDR II and QDR II+ SRAM Burst-length-of-two Interfaces 1.2.5. Pin Connection Guidelines Tables 1.2.6. PLLs and Clock Networks
1.2.2. Pin-out Rule Exceptions for ×36 Emulated QDR II and QDR II+ SRAM Interfaces in Arria II, Stratix III and Stratix IV Devices x
1.2.2.1. Timing Impact on x36 Emulation 1.2.2.2. Rules to Combine Groups 1.2.2.3. Determining the CQ/CQn Arrival Time Skew
1.2.3. Pin-out Rule Exceptions for RLDRAM II and RLDRAM 3 Interfaces x
1.2.3.1. Interfacing with ×9 RLDRAM II CIO Devices 1.2.3.2. Interfacing with ×18 RLDRAM II and RLDRAM 3 CIO Devices 1.2.3.3. Interfacing with RLDRAM II and RLDRAM 3 ×36 CIO Devices
1.2.5. Pin Connection Guidelines Tables x
1.2.5.1. DDR3 SDRAM With Leveling Interface Pin Utilization Applicable for Arria V GZ, Stratix III, Stratix IV, and Stratix V Devices 1.2.5.2. QDR II and QDR II+ SRAM Pin Utilization for Arria II, Arria V, Stratix III, Stratix IV, and Stratix V Devices 1.2.5.3. RLDRAM II CIO Pin Utilization for Arria II GZ, Arria V, Stratix III, Stratix IV, and Stratix V Devices  1.2.5.4. LPDDR2 Pin Utilization for Arria V, Cyclone V, and MAX 10 FPGA Devices 1.2.5.5. Additional Guidelines for Arria V GZ and Stratix V Devices 1.2.5.6. Additional Guidelines for Arria V ( Except Arria V GZ) Devices 1.2.5.7. Additional Guidelines for MAX 10 Devices 1.2.5.8. Additional Guidelines for Cyclone V Devices
1.2.6. PLLs and Clock Networks x
1.2.6.1. Number of PLLs Available in Intel® Device Families 1.2.6.2. Number of Enhanced PLL Clock Outputs and Dedicated Clock Outputs Available in Intel® Device Families 1.2.6.3. Number of Clock Networks Available in Intel® Device Families 1.2.6.4. Clock Network Usage in UniPHY-based Memory Interfaces—DDR2 and DDR3 SDRAM (1) (2) 1.2.6.5. Clock Network Usage in UniPHY-based Memory Interfaces—RLDRAM II, and QDR II and QDR II+ SRAM 1.2.6.6. PLL Usage for DDR, DDR2, and DDR3 SDRAM Without Leveling Interfaces 1.2.6.7. PLL Usage for DDR3 SDRAM With Leveling Interfaces
2. DDR2 and DDR3 SDRAM Board Design Guidelines x
2.1. Leveling and Dynamic Termination 2.2. DDR2 Terminations and Guidelines 2.3. DDR3 Terminations in Arria V, Cyclone V, Stratix III, Stratix IV, and Stratix V 2.4. Layout Approach 2.5. Channel Signal Integrity Measurement 2.6. Design Layout Guidelines 2.7. Package Deskew 2.8. Document Revision History
2.1. Leveling and Dynamic Termination x
2.1.1. Read and Write Leveling 2.1.2. Dynamic ODT 2.1.3. Dynamic On-Chip Termination 2.1.4. Dynamic On-Chip Termination in Stratix III and Stratix IV Devices 2.1.5. Dynamic OCT in Stratix V Devices
2.1.3. Dynamic On-Chip Termination x
2.1.3.1. FPGA Writing to Memory 2.1.3.2. FPGA Reading from Memory
2.2. DDR2 Terminations and Guidelines x
2.2.1. Termination for DDR2 SDRAM 2.2.2. DDR2 Design Layout Guidelines 2.2.3. General Layout Guidelines 2.2.4. Layout Guidelines for DDR2 SDRAM Interface
2.2.1. Termination for DDR2 SDRAM x
2.2.1.1. External Parallel Termination 2.2.1.2. On-Chip Termination 2.2.1.3. Recommended Termination Schemes
2.3. DDR3 Terminations in Arria V, Cyclone V, Stratix III, Stratix IV, and Stratix V x
2.3.1. Terminations for Single-Rank DDR3 SDRAM Unbuffered DIMM 2.3.2. Terminations for Multi-Rank DDR3 SDRAM Unbuffered DIMM 2.3.3. Terminations for DDR3 SDRAM Registered DIMM 2.3.4. Terminations for DDR3 SDRAM Load-Reduced DIMM 2.3.5. Terminations for DDR3 SDRAM Components With Leveling
2.3.5. Terminations for DDR3 SDRAM Components With Leveling x
2.3.5.1. DDR3 SDRAM Components With or Without Leveling
2.5. Channel Signal Integrity Measurement x
2.5.1. Importance of Accurate Channel Signal Integrity Information 2.5.2. Understanding Channel Signal Integrity Measurement 2.5.3. How to Enter Calculated Channel Signal Integrity Values 2.5.4. Guidelines for Calculating DDR3 Channel Signal Integrity
2.6. Design Layout Guidelines x
2.6.1. General Layout Guidelines 2.6.2. Layout Guidelines for DDR3 SDRAM Interfaces 2.6.3. Length Matching Rules 2.6.4. Spacing Guidelines 2.6.5. Layout Guidelines for DDR3 SDRAM Wide Interface (>72 bits)
2.6.5. Layout Guidelines for DDR3 SDRAM Wide Interface (>72 bits) x
2.6.5.1. Fly-By Network Design for Clock, Command, and Address Signals
2.7. Package Deskew x
2.7.1. Package Deskew Recommendation for Stratix V Devices 2.7.2. DQ/DQS/DM Deskew 2.7.3. Address and Command Deskew 2.7.4. Deskew Example 2.7.5. Package Migration 2.7.6. Package Deskew for RLDRAM II and RLDRAM 3
3. Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines x
3.1. General Layout Guidelines 3.2. Dual-Slot Unbuffered DDR2 SDRAM 3.3. Dual-Slot Unbuffered DDR3 SDRAM 3.4. Document Revision History
3.2. Dual-Slot Unbuffered DDR2 SDRAM x
3.2.1. Overview of ODT Control 3.2.2. DIMM Configuration 3.2.3. Dual-DIMM Memory Interface with Slot 1 Populated 3.2.4. Dual-DIMM with Slot 2 Populated 3.2.5. Dual-DIMM Memory Interface with Both Slot 1 and Slot 2 Populated 3.2.6. Dual-DIMM DDR2 Clock, Address, and Command Termination and Topology 3.2.7. Control Group Signals 3.2.8. Clock Group Signals
3.2.3. Dual-DIMM Memory Interface with Slot 1 Populated x
3.2.3.1. FPGA Writing to Memory 3.2.3.2. Write to Memory Using an ODT Setting of 150-ohm 3.2.3.3. Reading from Memory
3.2.4. Dual-DIMM with Slot 2 Populated x
3.2.4.1. FPGA Writing to Memory 3.2.4.2. Write to Memory Using an ODT Setting of 150-ohm 3.2.4.3. Reading from Memory
3.2.5. Dual-DIMM Memory Interface with Both Slot 1 and Slot 2 Populated x
3.2.5.1. FPGA Writing to Memory 3.2.5.2. Write to Memory in Slot 1 Using an ODT Setting of 75-ohm 3.2.5.3. Reading From Memory
3.3. Dual-Slot Unbuffered DDR3 SDRAM x
3.3.1. Comparison of DDR3 and DDR2 DQ and DQS ODT Features and Topology 3.3.2. Dual-DIMM DDR3 Clock, Address, and Command Termination and Topology 3.3.3. FPGA OCT Features
3.3.2. Dual-DIMM DDR3 Clock, Address, and Command Termination and Topology x
3.3.2.1. Address and Command Signals 3.3.2.2. Control Group Signals 3.3.2.3. Clock Group Signals
3.3.3. FPGA OCT Features x
3.3.3.1. Arria V, Cyclone V, Stratix III, Stratix IV, and Stratix V Devices 3.3.3.2. Arria II GX Devices
4. LPDDR2 SDRAM Board Design Guidelines x
4.1. LPDDR2 Guidance 4.2. Document Revision History
4.1. LPDDR2 Guidance x
4.1.1. LPDDR2 SDRAM Configurations 4.1.2. OCT Signal Terminations for Arria V and Cyclone V Devices 4.1.3. General Layout Guidelines 4.1.4. LPDDR2 Layout Guidelines
4.1.2. OCT Signal Terminations for Arria V and Cyclone V Devices x
4.1.2.1. Outputs from the FPGA to the LPDDR2 Component 4.1.2.2. Input to the FPGA from the LPDDR2 SDRAM Component 4.1.2.3. Termination Schemes
5. RLDRAM II and RLDRAM 3 Board Design Guidelines x
5.1. RLDRAM II Configurations 5.2. RLDRAM 3 Configurations 5.3. Signal Terminations 5.4. PCB Layout Guidelines 5.5. General Layout Guidelines 5.6. RLDRAM II and RLDRAM 3 Layout Guidelines 5.7. Layout Approach 5.8. Package Deskew for RLDRAM II and RLDRAM 3 5.9. Document Revision History
5.3. Signal Terminations x
5.3.1. Input to the FPGA from the RLDRAM Components 5.3.2. Outputs from the FPGA to the RLDRAM II and RLDRAM 3 Components 5.3.3. RLDRAM II Termination Schemes 5.3.4. RLDRAM 3 Termination Schemes
5.7. Layout Approach x
5.7.1. Arria V and Stratix V Board Setting Parameters
6. QDR II/II+ SRAM Board Design Guidelines x
6.1. QDR II SRAM Configurations 6.2. Signal Terminations 6.3. General Layout Guidelines 6.4. QDR II Layout Guidelines 6.5. QDR II SRAM Layout Approach 6.6. Package Deskew for QDR II 6.7. Document Revision History
6.2. Signal Terminations x
6.2.1. Output from the FPGA to the QDR II SRAM Component 6.2.2. Input to the FPGA from the QDR II SRAM Component 6.2.3. Termination Schemes
7. Implementing and Parameterizing Memory IP x
7.1. Design Flow 7.2. UniPHY-Based External Memory Interface IP 7.3. Document Revision History
7.1. Design Flow x
7.1.1. IP Catalog Design Flow 7.1.2. Platform Designer System Integration Tool Design Flow
7.1.1. IP Catalog Design Flow x
7.1.1.1. IP Catalog and Parameter Editor 7.1.1.2. Specifying Parameters for the IP Catalog Flow 7.1.1.3. Using Example Designs 7.1.1.4. Constraining the Design 7.1.1.5. Compiling the Design
7.1.1.4. Constraining the Design x
7.1.1.4.1. Adding Pins and DQ Group Assignments
7.1.2. Platform Designer System Integration Tool Design Flow x
7.1.2.1. Specify Parameters for the Platform Designer Flow 7.1.2.2. Completing the Platform Designer System
7.2. UniPHY-Based External Memory Interface IP x
7.2.1. Platform Designer Interfaces 7.2.2. Generated Files for Memory Controllers with the UniPHY IP 7.2.3. Parameterizing Memory Controllers 7.2.4. Board Settings 7.2.5. Controller Settings for UniPHY IP 7.2.6. Diagnostics for UniPHY IP
7.2.1. Platform Designer Interfaces x
7.2.1.1. DDR2 SDRAM Controller with UniPHY Intel FPGA IP Interfaces 7.2.1.2. DDR3 SDRAM Controller with UniPHY Intel FPGA IP Interfaces 7.2.1.3. LPDDR2 SDRAM Controller with UniPHY Intel FPGA IP Interfaces 7.2.1.4. QDR II and QDR II+ SRAM Controller with UniPHY Intel FPGA IP Interfaces 7.2.1.5. RLDRAM II Controller with UniPHY Intel FPGA IP Interfaces 7.2.1.6. RLDRAM 3 UniPHY Intel FPGA IP Interface
7.2.3. Parameterizing Memory Controllers x
7.2.3.1. PHY Settings for UniPHY IP 7.2.3.2. Memory Parameters for LPDDR2, DDR2 and DDR3 SDRAM Controller with UniPHY Intel FPGA IP 7.2.3.3. Memory Parameters for QDR II and QDR II+ SRAM Controller with UniPHY Intel FPGA IP 7.2.3.4. Memory Parameters for RLDRAM II Controller with UniPHY Intel FPGA IP 7.2.3.5. Memory Timing Parameters for DDR2, DDR3, and LPDDR2 SDRAM Controller with UniPHY Intel FPGA IP 7.2.3.6. Memory Timing Parameters for QDR II and QDR II+ SRAM Controller with UniPHY Intel FPGA IP 7.2.3.7. Memory Timing Parameters for RLDRAM II Controller with UniPHY Intel FPGA IP 7.2.3.8. Memory Parameters for RLDRAM 3 UniPHY Intel FPGA IP
7.2.3.2. Memory Parameters for LPDDR2, DDR2 and DDR3 SDRAM Controller with UniPHY Intel FPGA IP x
7.2.3.2.1. Memory Initialization Options for DDR2 7.2.3.2.2. Memory Initialization Options for DDR3 7.2.3.2.3. Memory Initialization Options for LPDDR2
7.2.4. Board Settings x
7.2.4.1. Setup and Hold Derating for UniPHY IP 7.2.4.2. Intersymbol Interference Channel Signal Integrity for UniPHY IP 7.2.4.3. Board Skews for UniPHY IP
7.2.4.3. Board Skews for UniPHY IP x
7.2.4.3.1. Board Skew Parameters for LPDDR2/DDR2/DDR3 SDRAM 7.2.4.3.2. Board Skew Parameters for QDR II and QDR II+ 7.2.4.3.3. Board Skew parameters for RLDRAM II and RLDRAM 3
8. Simulating Memory IP x
8.1. Simulation Options 8.2. Simulation Walkthrough with UniPHY IP 8.3. Document Revision History
8.2. Simulation Walkthrough with UniPHY IP x
8.2.1. Simulation Scripts 8.2.2. Preparing the Vendor Memory Model 8.2.3. Functional Simulation with Verilog HDL 8.2.4. Functional Simulation with VHDL 8.2.5. Simulating the Example Design 8.2.6. UniPHY Abstract PHY Simulation 8.2.7. PHY-Only Simulation 8.2.8. Post-fit Functional Simulation 8.2.9. Simulation Issues
8.2.8. Post-fit Functional Simulation x
8.2.8.1. Running Post-fit Simulation
9. Analyzing Timing of Memory IP x
9.1. Memory Interface Timing Components 9.2. FPGA Timing Paths 9.3. Timing Constraint and Report Files for UniPHY IP 9.4. Timing Analysis Description 9.5. Timing Report DDR 9.6. Report SDC 9.7. Calibration Effect in Timing Analysis 9.8. Timing Model Assumptions and Design Rules 9.9. Common Timing Closure Issues 9.10. Optimizing Timing 9.11. Timing Deration Methodology for Multiple Chip Select DDR2 and DDR3 SDRAM Designs 9.12. Performing I/O Timing Analysis 9.13. Document Revision History
9.1. Memory Interface Timing Components x
9.1.1. Source-Synchronous Paths 9.1.2. Calibrated Paths 9.1.3. Internal FPGA Timing Paths 9.1.4. Other FPGA Timing Parameters
9.2. FPGA Timing Paths x
9.2.1. Arria II Device PHY Timing Paths 9.2.2. Stratix III and Stratix IV PHY Timing Paths 9.2.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Timing paths
9.4. Timing Analysis Description x
9.4.1. UniPHY IP Timing Analysis
9.4.1. UniPHY IP Timing Analysis x
9.4.1.1. Address and Command 9.4.1.2. PHY or Core 9.4.1.3. PHY or Core Reset 9.4.1.4. Read Capture and Write 9.4.1.5. Read Resynchronization 9.4.1.6. DQS versus CK—Arria II GX and Cyclone IV Devices 9.4.1.7. Write Leveling tDQSS 9.4.1.8. Write Leveling tDSH/tDSS 9.4.1.9. DK versus CK (RLDRAM II with UniPHY) 9.4.1.10. Bus Turnaround Time
9.4.1.4. Read Capture and Write x
9.4.1.4.1. Stratix III 9.4.1.4.2. Arria II, Arria V, Cyclone V, Stratix IV and Stratix V
9.7. Calibration Effect in Timing Analysis x
9.7.1. Calibration Emulation for Calibrated Path 9.7.2. Calibration Error or Quantization Error 9.7.3. Calibration Uncertainties 9.7.4. Memory Calibration
9.8. Timing Model Assumptions and Design Rules x
9.8.1. Memory Clock Output Assumptions 9.8.2. Write Data Assumptions 9.8.3. Read Data Assumptions 9.8.4. DLL Assumptions 9.8.5. PLL and Clock Network Assumptions for Stratix III Devices
9.8.1. Memory Clock Output Assumptions x
9.8.1.1. Memory Clock Assumptions for Stratix III Devices
9.8.2. Write Data Assumptions x
9.8.2.1. Write Data Assumptions for Stratix III Devices
9.8.3. Read Data Assumptions x
9.8.3.1. Read Data Assumptions for Stratix III Devices
9.9. Common Timing Closure Issues x
9.9.1. Missing Timing Margin Report 9.9.2. Incomplete Timing Margin Report 9.9.3. Read Capture Timing 9.9.4. Write Timing 9.9.5. Address and Command Timing 9.9.6. PHY Reset Recovery and Removal 9.9.7. Clock-to-Strobe (for DDR and DDR2 SDRAM Only) 9.9.8. Read Resynchronization and Write Leveling Timing (for SDRAM Only)
9.11. Timing Deration Methodology for Multiple Chip Select DDR2 and DDR3 SDRAM Designs x
9.11.1. Multiple Chip Select Configuration Effects 9.11.2. Timing Deration using the Board Settings
9.11.1. Multiple Chip Select Configuration Effects x
9.11.1.1. ISI Effects 9.11.1.2. Calibration Effects 9.11.1.3. Board Effects
9.11.2. Timing Deration using the Board Settings x
9.11.2.1. Slew Rates 9.11.2.2. Slew Rate Setup, Hold, and Derating Calculation 9.11.2.3. Intersymbol Interference 9.11.2.4. Measuring Eye Reduction for Address/Command, DQ, and DQS Setup and Hold Time
9.12. Performing I/O Timing Analysis x
9.12.1. Performing I/O Timing Analysis with Third-Party Simulation Tools 9.12.2. Performing Advanced I/O Timing Analysis with Board Trace Delay Model
10. Debugging Memory IP x
10.1. Resource and Planning Issues 10.2. Interface Configuration Performance Issues 10.3. Functional Issue Evaluation 10.4. Timing Issue Characteristics 10.5. Verifying Memory IP Using the Signal Tap II Logic Analyzer 10.6. Hardware Debugging Guidelines 10.7. Categorizing Hardware Issues 10.8. EMIF Debug Toolkit Overview 10.9. Document Revision History
10.1. Resource and Planning Issues x
10.1.1. Dedicated DLL Resources 10.1.2. Dedicated IOE DQS Group Resources and Pins 10.1.3. Specific PLL Resources 10.1.4. Specific Global, Regional and Dual-Regional Clock Net Resources 10.1.5. Planning Your Design 10.1.6. Optimizing Design Utilization
10.2. Interface Configuration Performance Issues x
10.2.1. Interface Configuration Bottleneck and Efficiency Issues
10.3. Functional Issue Evaluation x
10.3.1. Correct Combination of the Quartus Prime Software and ModelSim* - Intel® FPGA Edition Device Models 10.3.2. Intel® IP Memory Model 10.3.3. Vendor Memory Model 10.3.4. Insufficient Memory in Your PC 10.3.5. Transcript Window Messages 10.3.6. Passing Simulation 10.3.7. Modifying the Example Driver to Replicate the Failure
10.4. Timing Issue Characteristics x
10.4.1. Evaluating FPGA Timing Issues 10.4.2. Evaluating External Memory Interface Timing Issues
10.5. Verifying Memory IP Using the Signal Tap II Logic Analyzer x
10.5.1. Signals to Monitor with the Signal Tap II Logic Analyzer
10.6. Hardware Debugging Guidelines x
10.6.1. Create a Simplified Design that Demonstrates the Same Issue 10.6.2. Measure Power Distribution Network 10.6.3. Measure Signal Integrity and Setup and Hold Margin 10.6.4. Vary Voltage 10.6.5. Use Freezer Spray and Heat Gun 10.6.6. Operate at a Lower Speed 10.6.7. Determine Whether the Issue Exists in Previous Versions of Software 10.6.8. Determine Whether the Issue Exists in the Current Version of Software 10.6.9. Try A Different PCB 10.6.10. Try Other Configurations 10.6.11. Debugging Checklist
10.7. Categorizing Hardware Issues x
10.7.1. Signal Integrity Issues 10.7.2. Hardware and Calibration Issues
10.7.1. Signal Integrity Issues x
10.7.1.1. Characteristics of Signal Integrity Issues 10.7.1.2. Evaluating SignaI Integrity Issues
10.7.1.2. Evaluating SignaI Integrity Issues x
10.7.1.2.1. Skew 10.7.1.2.2. Crosstalk 10.7.1.2.3. Power System 10.7.1.2.4. Clock Signals 10.7.1.2.5. Read Data Valid Window and Eye Diagram 10.7.1.2.6. Write Data Valid Window and Eye Diagram 10.7.1.2.7. OCT and ODT Usage
10.7.2. Hardware and Calibration Issues x
10.7.2.1. Evaluating Hardware and Calibration Issues
10.7.2.1. Evaluating Hardware and Calibration Issues x
10.7.2.1.1. Write Timing Margin 10.7.2.1.2. Read Timing Margin 10.7.2.1.3. Address and Command Timing Margin 10.7.2.1.4. Resynchronization Timing Margin 10.7.2.1.5. Postamble Timing Issues and Margin 10.7.2.1.6. Intermittent Issue Evaluation
11. Optimizing the Controller x
11.1. Factors Affecting Efficiency 11.2. Ways to Improve Efficiency 11.3. Document Revision History
11.1. Factors Affecting Efficiency x
11.1.1. Interface Standard 11.1.2. Bank Management Efficiency 11.1.3. Data Transfer
11.2. Ways to Improve Efficiency x
11.2.1. DDR2 SDRAM Controller 11.2.2. Auto-Precharge Commands 11.2.3. Additive Latency 11.2.4. Bank Interleaving 11.2.5. Command Queue Look-Ahead Depth 11.2.6. Additive Latency and Bank Interleaving 11.2.7. User-Controlled Refresh 11.2.8. Frequency of Operation 11.2.9. Burst Length 11.2.10. Series of Reads or Writes 11.2.11. Data Reordering 11.2.12. Starvation Control 11.2.13. Command Reordering 11.2.14. Bandwidth 11.2.15. Efficiency Monitor
12. PHY Considerations x
12.1. Core Logic and User Interface Data Rate 12.2. Hard and Soft Memory PHY 12.3. Sequencer 12.4. PLL, DLL and OCT Resource Sharing 12.5. Pin Placement Consideration 12.6. Document Revision History
13. Power Estimation Methods for External Memory Interfaces x
13.1. Performing Vector-Based Power Analysis with the Power Analyzer 13.2. Document Revision History
1. Planning Pin and FPGA Resources
2. DDR2 and DDR3 SDRAM Board Design Guidelines
3. Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines
4. LPDDR2 SDRAM Board Design Guidelines
5. RLDRAM II and RLDRAM 3 Board Design Guidelines
6. QDR II/II+ SRAM Board Design Guidelines
7. Implementing and Parameterizing Memory IP
8. Simulating Memory IP
9. Analyzing Timing of Memory IP
10. Debugging Memory IP
11. Optimizing the Controller
12. PHY Considerations
13. Power Estimation Methods for External Memory Interfaces

9.4.1.4.1. Stratix III

This topic details the timing margins, such as the read data and write data timing paths, which the Timing Analyzer callates for Stratix III designs. Timing paths internal to the FPGA are either guaranteed by design and tested on silicon, or analyzed by the Timing Analyzer using corresponding timing constraints.

For design guidelines about implementing and analyzing your external memory interface using the PHY in Stratix III and Stratix IV devices, refer to the design tutorials on the List of designs using Intel FPGA External Memory IP page of the Intel® FPGA Wiki page.

Timing margins for chip-to-chip data transfers can be defined as:

Margin = bit period – transmitter uncertainties – receiver requirements

where:

  • Sum of all transmitter uncertainties = transmitter channel-to-channel skew (TCCS).

    The timing difference between the fastest and slowest output edges on data signals, including tCO variation, clock skew, and jitter. The clock is included in the TCCS measurement and serves as the time reference.

  • Sum of all receiver requirements = receiver sampling window (SW) requirement.

    The period of time during which the data must be valid to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window.

  • Receiver skew margin (RSKM) = margin or slack at the receiver capture register.

For TCCS and SW specifications, refer to the DC and Switching Characteristics chapter of the Stratix III Device Handbook.

The following figure relates this terminology to a timing budget diagram.

Figure 60. Sample Timing Budget Diagram


The timing budget regions marked “½ × TCCS” represent the latest data valid time and earliest data invalid times for the data transmitter. The region marked sampling window is the time required by the receiver during which data must stay stable. This sampling window comprises the following:

  • Internal register setup and hold requirements
  • Skew on the data and clock nets within the receiver device
  • Jitter and uncertainty on the internal capture clock
Note: The sampling window is not the capture margin or slack, but instead the requirement from the receiver. The margin available is denoted as RSKM.

The simple example illustrated in the preceding figure does not consider any board level uncertainties, assumes a center-aligned capture clock at the middle of the receiver sampling window region, and assumes an evenly distributed TCCS with respect to the transmitter clock pin. In this example, the left end of the bit period corresponds to time t = 0, and the right end of the bit period corresponds to time t = TUI (where TUI stands for time unit interval). Therefore, the center-aligned capture clock at the receiver is best placed at time t = TUI/2.

Therefore:

the total margin = 2 × RSKM = TUI – TCCS – SW.

Consider the case where the clock is not center-aligned within the bit period (clock phase shift = P), and the transmitter uncertainties are unbalanced (TCCSLEAD and TCCSLAG). TCCSLEAD is defined as the skew between the clock signal and latest data valid signal. TCCSLAG is defined as the skew between the clock signal and earliest data invalid signal. Also, the board level skew across data and clock traces are specified as tEXT. For this condition, you should compute independent setup and hold margins at the receiver (RSKMSETUP and RSKMHOLD). In this example, the sampling window requirement is split into a setup side requirement (SWSETUP) and hold side (SWHOLD) requirement. The following figure illustrates the timing budget for this condition. A timing budget similar to that shown is used for Stratix III FPGA read and write data timing paths.

Figure 61. Sample Timing Budget with Unbalanced (TCCS and SW) Timing Parameters


Therefore:

Setup margin = RSKMSETUP = P – TCCSLEAD – SWSETUP – tEXT

Hold margin = RSKMHOLD = (TUI – P) – TCCSLAG – SWHOLD – tEXT

The timing budget illustrated in the first figure with balanced timing parameters applies for calibrated paths where the clock is dynamically center-aligned within the data valid window. The timing budget illustrated in the second figure with unbalanced timing parameters applies for circuits that employ a static phase shift using a DLL or PLL to place the clock within the data valid window.

Related Information

Read Capture

Memory devices provide edge-aligned DQ and DQS outputs to the FPGA during read operations. Stratix III FPGAs center-aligns the DQS strobe using static DLL-based delays. Stratix III devices use a source synchronous circuit for data capture.

When applying this methodology to read data timing, the memory device is the transmitter and the FPGA device is the receiver.

The transmitter channel-to-channel skew on outputs from the memory device is available from the corresponding device data sheet. Let us examine the TCCS parameters for a DDR2 SDRAM component.

For DQS-based capture:

  • The time between DQS strobe and latest data valid is defined as tDQSQ
  • The time between earliest data invalid and next strobe is defined as tQHS
  • Based on earlier definitions, TCCSLEAD = tDQSQ and TCCSLAG = tQHS

The sampling window at the receiver, the FPGA, includes several timing parameters:

  • Capture register micro setup and micro hold time requirements
  • DQS clock uncertainties because of DLL phase shift error and phase jitter
  • Clock skew across the DQS bus feeding DQ capture registers
  • Data skew on DQ paths from pin to input register including package skew

For TCCS and SW specifications, refer to the DC and Switching Characteristics chapter of the Stratix III Device Handbook.

The following figure shows the timing budget for a read data timing path.

Figure 62. Timing Budget for Read Data Timing Path


The following table lists a read data timing analysis for a Stratix III –2 speed‑grade device interfacing with a 400-MHz DDR2 SDRAM component.

Table 83.  Read Data Timing Analysis for Stratix III Device with a 400-MHz DDR2 SDRAM  (1)   

Parameter

Specifications

Value (ps)

Description

Memory Specifications  (1)

tHP

1250

Average half period as specified by the memory data sheet, tHP = 1/2 * tCK

tDCD

50

Duty cycle distortion = 2% × tCK = 0.02 × 2500 ps

tDQSQ

200

Skew between DQS and DQ from memory

tQHS

300

Data hold skew factor as specified by memory

FPGA Specifications

tSW_SETUP

181

FPGA sampling window specifications for a given configuration (DLL mode, width, location, and so on.)

tSW_HOLD

306

Board Specifications

tEXT

20

Maximum board trace variation allowed between any two signal traces (user specified parameter)

Timing Calculations

tDVW

710

tHP – tDCD – tDQSQ – tQHS – 2 × tEXT

tDQS_PHASE_DELAY

500

Ideal phase shift delay on DQS capture strobe

= (DLL phase resolution × number of delay stages × tCK) / 360° = (36° × 2 stages × 2500 ps)/360° = 500 ps

Results

Setup margin

99

RSKMSETUP = tDQSQ_PHASE_DELAY – tDQSQ – tSW_SETUP – tEXT

Hold margin

74

RSKMHOLD = tHP – tDCD – tDQS_PHASE_DELAY – tQHS – tSW_HOLD – tEXT

Notes to Table:

  1. This sample calculation uses memory timing parameters from a 72-bit wide 256-MB micron MT9HTF3272AY-80E 400‑MHz DDR2 SDRAM DIMM.

Write Capture

During write operations, the FPGA generates a DQS strobe and a center‑aligned DQ data bus using multiple PLL-driven clock outputs. The memory device receives these signals and captures them internally. The Stratix III family contains dedicated DDIO (double data rate I/O) blocks inside the IOEs.

For write operations, the FPGA device is the transmitter and the memory device is the receiver. The memory device’s data sheet specifies data setup and data hold time requirements based on the input slew rate on the DQ/DQS pins. These requirements make up the memory sampling window, and include all timing uncertainties internal to the memory.

Output skew across the DQ and DQS output pins on the FPGA make up the TCCS specification. TCCS includes contributions from numerous internal FPGA circuits, including:

  • Location of the DQ and DQS output pins
  • Width of the DQ group
  • PLL clock uncertainties, including phase jitter between different output taps used to center-align DQS with respect to DQ
  • Clock skew across the DQ output pins, and between DQ and DQS output pins
  • Package skew on DQ and DQS output pins

Refer to the DC and Switching Characteristics chapter of the Stratix III Device Handbook for TCCS and SW specifications.

The following figure illustrates the timing budget for a write data timing path.

Figure 63. Timing Budget for Write Data Timing Path


The following table lists a write data timing analysis for a Stratix III –2 speed‑grade device interfacing with a DDR2 SDRAM component at 400 MHz. This timing analysis assumes the use of a differential DQS strobe with 2.0‑V/ns edge rates on DQS, and 1.0‑V/ns edge rate on DQ output pins. Consult your memory device’s data sheet for derated setup and hold requirements based on the DQ/DQS output edge rates from your FPGA.

.

Table 84.  Write Data Timing Analysis for 400-MHz DDR2 SDRAM Stratix III Device   (1)   

Parameter

Specifications

Value (ps)

Description

Memory Specifications  (1)

tHP

1250

Average half period as specified by the memory data sheet

tDSA

250

Memory setup requirement (derated for DQ/DQS edge rates and VREF reference voltage)

tDHA

250

Memory hold requirement (derated for DQ/DQS edge rates and VREF reference voltage)

FPGA Specifications

TCCSLEAD

229

FPGA transmitter channel-to-channel skew for a given configuration (PLL setting, location, and width).

TCCSLAG

246

Board Specifications

tEXT

20

Maximum board trace variation allowed between any two signal traces (user specified parameter)

Timing Calculations

tOUTPUT_CLOCK _OFFSET

625

Output clock phase offset between DQ & DQS output clocks = 90°.

tOUTPUT_CLOCK_OFFSET = (output clock phase DQ and DQS offset x tCK)/360° = (90° x 2500)/360° = 625

TX_DVWLEAD

396

Transmitter data valid window = tOUTPUT_CLOCK_OFFSET – TCCSLEAD

TX_DVWLAG

379

Transmitter data valid window = tHP - tOUTPUT_CLOCK_OFFSET – TCCSLAG

Results

Setup margin

126

TX_DVWLEAD – tEXT – tDSA

Hold margin

109

TX_DVWLAG – tEXT – tDHA

Notes to Table:

  1. This sample calculation uses memory timing parameters from a 72-bit wide 256-MB micron MT9HTF3272AY-80E 400-MHz DDR2 SDRAM DIMM
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