Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Public
Document Table of Contents

4.1.7.1. Pin Mapping in Stratix V Devices

Table 24.  Mapping Between the Input Clock Pins, PLL Counter Outputs, and Clock Control Block Inputs
Clock Fed by
inclk[0] and inclk[1] Any of the four dedicated clock pins on the same side of the Stratix® V device.
inclk[2] PLL counters C0 and C2 from the two center PLLs on the same side of the Stratix® V devices.
inclk[3] PLL counters C1 and C3 from the two center PLLs on the same side of the Stratix® V devices.
Note: You cannot use corner PLLs for dynamic clock control selection.