Cyclone V SoC Power Optimization

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ID 683713
Date 2/09/2015
Public
Document Table of Contents
Document Table of Contents x
1. Cyclone V SoC Power Optimization
1. Cyclone V SoC Power Optimization x
1.1. Power Reduction 1.2. HPS Power Reduction Methods 1.3. FPGA Power Reduction Methods 1.4. Power Optimization Summary 1.5. Appendix: Power Measurement Techniques for Cyclone V SoC Dev Kit
1.2. HPS Power Reduction Methods x
1.2.1. MPU 1.2.2. Peripherals 1.2.3. HPS Power Reduction Summary
1.2.1. MPU x
1.2.1.1. HPS Method 1: Fit Code in Cache 1.2.1.2. HPS Method 2: Processor Standby Modes and Dynamic Clock Gating 1.2.1.3. HPS Method 3: CPU1 in WFI/WFE or Standby Loop 1.2.1.4. HPS Method 4: Lowering CPU Frequency
1.2.2. Peripherals x
1.2.2.1. HPS Method 5: Energy Efficient Ethernet 1.2.2.2. HPS Method 6: USB Power Management 1.2.2.3. HPS Method 7: Unused Peripherals in Reset
1.3. FPGA Power Reduction Methods x
1.3.1. FPGA Power Consumption 1.3.2. FPGA Portion Power Down 1.3.3. FPGA Power Off Step 1: Board Design (Power Rail) Choices 1.3.4. FPGA Power Off Step 2: Quiet FPGA 1.3.5. FPGA Power Off Step 3: Power Off the FPGA 1.3.6. FPGA Power Off Step 4: Wake up Event for Power on and FPGA Configuration 1.3.7. FPGA Power Off Step 5: Power On and FPGA Reconfiguration Time Considerations
1.5. Appendix: Power Measurement Techniques for Cyclone V SoC Dev Kit x
1.5.1. Power Monitoring and Measurement 1.5.2. Cyclone V SoC Development Kit Power Management ICs 1.5.3. Cyclone V SoC Development Kit Power Monitor Application 1.5.4. LTC LTpower Play Tool 1.5.5. Using the LTC2978A Linux Driver 1.5.6. Power Measurement Results on Cyclone V SoC Development Kit 1.5.7. Document Revision History
1.5.3. Cyclone V SoC Development Kit Power Monitor Application x
1.5.3.1. Starting the Application 1.5.3.2. Windows Instructions 1.5.3.3. Linux Instructions
1.5.4. LTC LTpower Play Tool x
1.5.4.1. Requirements 1.5.4.2. LTC Video Tutorial
1.5.5. Using the LTC2978A Linux Driver x
1.5.5.1. Compiling the Driver 1.5.5.2. Using the Driver
1. Cyclone V SoC Power Optimization

1.2.1.4. HPS Method 4: Lowering CPU Frequency

Lowering CPU frequency can reduce the amount of power the MPU consumes as shown in the following table:

Table 1.  Power Reduction for Different CPU Frequencies
Frequency Change Power Savings
From: To: Approximate Power Reduction:
800 MHz 400 MHz 190 mW
400 MHz 200 MHz 90 mW
200 MHz 100 MHz 50 mW

The Rocketboards Preloader Clocking Customization link indicates, changing SDRAM frequency is a separate exercise and should only be done using Qsys.

Note: Be aware that changes to the PLL VCOs can affect certain peripheral speeds. On the Preloader Clocking Customization link you can use the value generating tables to check if the desired peripheral speeds are met before making changes and recompiling the Preloader.
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