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1.1. List of Abbreviations
1.2. Introduction
1.3. Intel® Stratix® 10 Early Power Estimator Tool (EPE)
1.4. Intel® Stratix® 10 FPGA Package Physical Design
1.5. Physical Package Structure
1.6. Intel® Stratix® 10 FPGA Thermal Design Parameters
1.7. Intel® Stratix® 10 Compact Thermal Model (CTM)
1.8. Intel® Stratix® 10 Temperature Sensing Diodes (TSD)
1.9. Intel® Stratix® 10 Thermal Design Process
1.10. Early Power Estimator (EPE)
1.11. Transceiver Channel Spreading
1.12. Thermal Parameter Dependencies
1.13. Intel® Stratix® 10 Thermal Design Example
1.14. Document Revision History for AN 787: Intel® Stratix® 10 Thermal Modeling and Management with the Early Power Estimator
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1.7. Intel® Stratix® 10 Compact Thermal Model (CTM)
The Intel® Stratix® 10 FPGA thermal analysis requires the use of its CTMs in a Computational Fluid Dynamic (CFD) tool. The results of the CFD analysis are only valid to determine the core fabric power and IHS temperature. These values are used to determine the junction temperature of all the dies.
This methodology is used because the construction of the CTM does not capture the details of transceiver channel placements; therefore, it cannot be used to predict the correct junction temperature of a transceiver die. The transceiver junction temperature is calculated using the total power dissipation, IHS temperature and thermal resistance of each die which will be covered in later sections.
The Intel® Stratix® 10 CTMs are offered in the following formats:
- Icepak* from ANSYS
- Flotherm* from Mentor Graphics
- 6SigmaET* from Future Facilities
- Thermal Analysis* from SolidWorks