Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

5.12. Correctable Error Mask Register

Table 66.  Correctable Error Mask Register - 0x114

Bits

Register Description

Default Value

Access

[31:14] Reserved 0

RO

[13]

When set, masks an Advisory Non-Fatal Error

0

RW

[12]

When set, masks a Replay Timeout

0

RW

[11:9]

Reserved

0

RO

[8]

When set, masks a Replay Number Rollover

0

RW

[7]

When set, masks a Bad DLLP received

0

RW

[6]

When set, masks a Bad TLP received 0

RW

[5:1]

Reserved

0

RO

[0]

When set, masks a Receiver Error

0

RW