Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

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ID 683488
Date 5/02/2016
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the SR-IOV DMA Example Design 3. Parameter Settings 4. Interfaces and Signal Descriptions 5. Registers 6. Programming and Testing SR-IOV Bridge MSI Interrupts 7. Error Handling 8. IP Core Architecture 9. Design Implementation 10. Transceiver PHY IP Reconfiguration 11. Debugging A. Frequently Asked Questions for PCI Express B. Transaction Layer Packet (TLP) Header Formats C. Stratix V Avalon-ST with SR-IOV Interface for PCIe Solutions User Guide Archive 12. Document Revision History
1. Datasheet x
1.1. Stratix® V Avalon-ST Interface with SR-IOV for PCIe Datasheet 1.2. Release Information 1.3. Device Family Support 1.4. Design Examples for SR-IOV 1.5. Debug Features 1.6. IP Core Verification 1.7. Performance and Resource Utilization 1.8. Recommended Speed Grades for SR-IOV Interface 1.9. Creating a Design for PCI Express
1.1. Stratix® V Avalon-ST Interface with SR-IOV for PCIe Datasheet x
1.1.1. SR-IOV Features
1.6. IP Core Verification x
1.6.1. Compatibility Testing Environment
2. Getting Started with the SR-IOV DMA Example Design x
2.1. Generating the Example Design Testbench 2.2. Understanding the Generated Files and Directories 2.3. Simulating the SR-IOV Example Design 2.4. Running a Gate-Level Simulation 2.5. Understanding the DMA Functionality 2.6. Compiling the Example Design with the Quartus® Prime Software 2.7. Using the IP Catalog To Generate Your Stratix V Hard IP for PCI Express as a Separate Component
3. Parameter Settings x
3.1. System Settings 3.2. SR-IOV System Settings 3.3. Base Address Register (BAR) Settings 3.4. SR-IOV Device Identification Registers 3.5. Interrupt Capabilities 3.6. PCI Express and PCI Capabilities Parameters 3.7. PHY Characteristics 3.8. Simulation Options
3.6. PCI Express and PCI Capabilities Parameters x
3.6.1. Device Capabilities 3.6.2. Error Reporting 3.6.3. Link Capabilities 3.6.4. Slot Capabilities 3.6.5. Power Management
4. Interfaces and Signal Descriptions x
4.1. Avalon-ST TX Interface 4.2. Component-Specific Avalon-ST Interface Signals 4.3. Avalon-ST RX Interface 4.4. BAR Hit Signals 4.5. Configuration Status Interface 4.6. Clock Signals 4.7. Function-Level Reset Interface 4.8. Interrupt Interface 4.9. Configuration Extension Bus (CEB) Interface 4.10. Implementing MSI-X Interrupts 4.11. Local Management Interface (LMI) Signals 4.12. Reset, Status, and Link Training Signals 4.13. Transceiver Reconfiguration 4.14. Serial Data Signals 4.15. Test Signals 4.16. PIPE Interface Signals
4.9. Configuration Extension Bus (CEB) Interface x
4.9.1. Vital Product Data (VPD) Capability
4.9.1. Vital Product Data (VPD) Capability x
4.9.1.1. Determine the Pointer Address of an External Capability Register 4.9.1.2. VPD Capability Implementation
4.14. Serial Data Signals x
4.14.1. Physical Layout of Hard IP In Stratix V Devices 4.14.2. Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. PCI and PCI Express Configuration Space Registers 5.3. MSI Registers 5.4. MSI-X Capability Structure 5.5. Power Management Capability Structure 5.6. PCI Express Capability Structure 5.7. Advanced Error Reporting (AER) Enhanced Capability Header Register 5.8. Uncorrectable Error Status Register 5.9. Uncorrectable Error Mask Register 5.10. Uncorrectable Error Severity Register 5.11. Correctable Error Status Register 5.12. Correctable Error Mask Register 5.13. Advanced Error Capabilities and Control Register 5.14. Header Log Registers 0-3 5.15. SR-IOV Virtualization Extended Capabilities Registers 5.16. Virtual Function Registers
5.2. PCI and PCI Express Configuration Space Registers x
5.2.1. Type 0 Configuration Space Registers 5.2.2. PCI and PCI Express Configuration Space Register Content 5.2.3. Interrupt Line and Interrupt Pin Register
5.15. SR-IOV Virtualization Extended Capabilities Registers x
5.15.1. SR-IOV Virtualization Extended Capabilities Registers Address Map 5.15.2. ARI Enhanced Capability Header 5.15.3. SR-IOV Enhanced Capability Registers 5.15.4. Initial VFs and Total VFs Registers 5.15.5. VF Device ID Register 5.15.6. Page Size Registers 5.15.7. VF Base Address Registers (BARs) 0-5 5.15.8. Secondary PCI Express Extended Capability Header 5.15.9. Lane Status Registers
6. Programming and Testing SR-IOV Bridge MSI Interrupts x
6.1. Setting Up and Verifying MSI Interrupts 6.2. Masking MSI Interrupts 6.3. Dropping a Pending MSI Interrupt
7. Error Handling x
7.1. Physical Layer Errors 7.2. Data Link Layer Errors 7.3. Transaction Layer Errors 7.4. Error Reporting and Data Poisoning 7.5. Uncorrectable and Correctable Error Status Bits
8. IP Core Architecture x
8.1. Data Link Layer 8.2. Physical Layer 8.3. Top-Level Interfaces 8.4. Physical and Virtual Function Address Assignments 8.5. Stratix V Hard IP for PCI Express with Single-Root I/O Virtualization (SR-IOV)
8.3. Top-Level Interfaces x
8.3.1. Avalon-ST Interface 8.3.2. Clocks and Reset 8.3.3. Transceiver Reconfiguration 8.3.4. Interrupts 8.3.5. PIPE
9. Design Implementation x
9.1. Making Analog QSF Assignments Using the Assignment Editor 9.2. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 9.3. Recommended Reset Sequence to Avoid Link Training Issues 9.4. SDC Timing Constraints
10. Transceiver PHY IP Reconfiguration x
10.1. Connecting the Transceiver Reconfiguration Controller IP Core 10.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
11. Debugging x
11.1. Setting Up Simulation 11.2. Hardware Bring-Up Issues 11.3. Link Training 11.4. Use Third-Party PCIe Analyzer 11.5. BIOS Enumeration Issues
11.1. Setting Up Simulation x
11.1.1. Changing Between Serial and PIPE Simulation 11.1.2. Using the PIPE Interface for Gen1 and Gen2 Variants 11.1.3. Viewing the Important PIPE Interface Signals 11.1.4. Disabling the Scrambler for Gen1 and Gen2 Simulations 11.1.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations 11.1.6. Changing between the Hard and Soft Reset Controller
11.3. Link Training x
11.3.1. Debugging Link that Fails To Reach L0
B. Transaction Layer Packet (TLP) Header Formats x
B.1. TLP Packet Formats without Data Payload B.2. TLP Packet Formats with Data Payload
12. Document Revision History x
12.1. Document Revision History for the Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide
1. Datasheet
2. Getting Started with the SR-IOV DMA Example Design
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Programming and Testing SR-IOV Bridge MSI Interrupts
7. Error Handling
8. IP Core Architecture
9. Design Implementation
10. Transceiver PHY IP Reconfiguration
11. Debugging
A. Frequently Asked Questions for PCI Express
B. Transaction Layer Packet (TLP) Header Formats
C. Stratix V Avalon-ST with SR-IOV Interface for PCIe Solutions User Guide Archive
12. Document Revision History

5.16. Virtual Function Registers

The SR-IOV Bridge implements the PCI and PCI Express Configuration Spaces for a maximum of 128 Virtual Functions . The VF registers available are a subset of the PF registers. For example, the VFs do not implement the Link Capabilities 2 register. The definitions of VF registers are the same as PF registers. For additional details, refer to the PCI Express Base Specification 3.0.
Note: The following Virtual Function register map is applicable to all revisions of the Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe from the 18.1 release of Intel® Quartus® Prime onward.
Table 85.   Virtual Function Registers - Differences from PF

Address (hex)

Name

Description

0x000 Vendor ID and Device ID Register Vendor ID Register and Device ID Registers defined in PCI Express Base Specification 3.0 . These registers are hardwired to all 1s.
0x004 Command and Status Register PCI Command and Status Registers. Refer to Command and Status Register for VFs for descriptions of the implemented fields.
0x008 Revision ID and Class Code Register PCI Revision ID and Class Code Registers defined in PCI Express Base Specification 3.0 . The VF has the same settings and access as PF0.
0x00C BIST, Header Type, Latency Timer and Cache Line Size Registers Contains the following registers defined in the PCI Express Base Specification 3.0 : BIST Register, Header Type Register, Latency Timer, Cache Line Size Register. These registers are hardwired to all 0s for VFs.
0x010:

0x028

Reserved N/A
0x02C Subsystem Vendor ID and Subsystem ID Registers PCI Subsystem Vendor ID and Subsystem ID Registers. The VF has the same settings and access as PF0.
0x030 Reserved N/A
0x034 Capabilities Pointer This register points to the first Capability Structure in the PCI Configuration Space. For VFs, it points to the MSI-X capability.
0x038:

0x03C

Reserved N/A

MSI-X Capability Structure

MSI-X Control Register

Contains the MSI-X Message Control Register, Capability ID for MSI-X, and the next capability pointer. The VF has the same fields and access as the parent PF.

MSI-X Table Offset

Points to the MSI-X Table in memory. Also specifies the BAR corresponding to the memory segment where the MSI-X Table resides. The VF has the same fields and access as the PF.

MSI-X PBA Offset

Points to the MSI-X Pending Bit Array in memory. Also, specifies the BAR corresponding to the memory segment where the PBA Array resides. The VF has the same fields and access as the parent PF.

PCI Express Capability Structure

PCI Express Capability List Register

Capability ID, PCI Express Capabilities Register, and the next capability pointer. Refer to cite="PCI Express Capability List Register for VFs" for descriptions of the implemented fields.

PCI Express Device Capabilities Register

PCI Express Device Capabilities Register. The VF Device Capabilities Register supports the same fields as the PF Device Capabilities Register.

PCI Express Device Control and Status Registers

The lower 16 bits implement the PCI Express Device Control Register. The upper 16 bits implement the Device Status Register. Refer to PCI Express Devices Control and Status Registers for VFs for descriptions of the implemented fields.

Link Capabilities Register

A read to any VF with this address returns the Link Capabilities Register settings of the parent PF.

Link Control and Status Registers

This register is not implemented for VFs, and reads as all 0s.

Device Capabilities 2 Registers

A read to any VF with this address returns the Device Capabilities 2 Register settings of the parent PF.

Device Control 2 and Status 2 Registers

This register is not implemented for VFs. A read to this address returns all 0s.

Link Capabilities 2 Register

This register is not implemented for VFs. A read to this address returns all 0s.

Link Control 2 and Status 2 Registers This register contains control and status bits for the PCIe link. For VFs, bit[16] stores the current de-emphasis level setting for the parent PF. All other bits are reserved.

Alternate RID (ARI) Capability Structure

0x100

ARI Enhanced Capability Header

PCI Express Extended Capability ID for ARI and Next Capability pointer. The Next Capability pointer points to NULL.

0x104

ARI Capability Register, ARI Control Register

This register is not implemented for VFs. A read to this address returns all 0s.

Table 86.  Command and Status Register for VFs - 0x004

Bits

Register Description

Default Value

Access

Command Register

[1:0] Reserved. 0 RO
[2] Bus Master enable. When set, the VF can generate transactions as a bus master. 0 RW
[15:3] Reserved. 0 RO

Status Register

[3:0] Reserved. 0 RO
[4] Indicates the presence of PCI Extended Capabilities. This bit is hardwired to 1. 0 RW1C
[7:5] Reserved. 0 RO
[8] Master Data Parity Error. Enabled when the PF PCI Command Register Parity Error Response bit is set. When set, indicates one of the following conditions:
  • The device has received a Poisoned Completion from the link for this VF
  • This VF has transmitted a Poisoned Memory Write request on the link
RW1C
[10:9] Reserved. 0 RO
[11] Signal Target Abort. When set, this VF has sent a Completion to the link with Completer Abort (CA) stats. 0 RW1C
[12] Received Target Abort. When set, indicates that this VF has received a Completion from the link with the CA status. 0 RW1C
[13] Received Master Abort. When set, indicates that this VF has received a Completion from the link with the Unsupported Request (UR) status. 0 RW1C
[14] Signaled System Error. When set, indicates that this VF has transmitted a Fatal or Non-Fatal error message on the link to the Root Complex. Enabled when the PF PCI Command Register SERR Enable bit is set. 0 RW1C
[15] Received Master Abort. When set, indicates the VF has received a Completion from the link with the Unsupported Request (UR) status. 0 RW1C
Table 87.  PCI Express Capability List Register for VFs -

Bits

Register Description

Default Value

Access

[31:19] Hardwired to 0. 2 RO
[18:16] Version ID: Version of PCI Express Capability. 0 RW
[15:8] Next Capability Pointer: Points to NULL. 0 RO
[7:0] Capability ID assigned by PCI-SIG. 0x10 RO
Table 88.  PCI Express Device Control and Status Registers for VFs -

Bits

Register Description

Default Value

Access

Control Register

[14:0] Reserved. 0 RO
[15] Function-Level Reset. Writing a 1 to this bit generates a Function-Level Reset for this VF. Only functional when the PF Device Capabilities Register FLR Capable bit is set. This bit always reads as 0. 0 RW

Status Register

[16] Correctable Error Detected. 0 RW1C
[17] Non-Fatal Error Detected. 0 RW1C
[18] Fatal Error Detected. 0 RW1C
[19] Unsupported Request Detected. 0 RW1C
[20] Not implemented. 0 RO
[21] Transaction Pending. When set, indicates that a Non-Posted request issued by this VF is still pending. 0 RO
[31:22] Reserved. 0 RO
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