AN 744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices

Download PDF
ID 683785
Date 5/13/2016
Public
Document Table of Contents
Document Table of Contents x
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices x
1.1. Block Diagrams 1.2. Design Components 1.3. Design Parameters 1.4. Hardware and Software Requirements 1.5. Using the Reference Design 1.6. Upgrading the Components 1.7. Testbench 1.8. Interface Signals 1.9. Configuration Registers 1.10. Document Revision History
1.7. Testbench x
1.7.1. Testbench Files 1.7.2. Simulating the Testbench 1.7.3. Test Case: Design With the IEEE 1588v2 Feature 1.7.4. Test Case: Design Without the IEEE 1588v2 Feature
1.8. Interface Signals x
1.8.1. Packet Classifier Interface Signals 1.8.2. ToD Interface Signals
1.9. Configuration Registers x
1.9.1. ToD Registers 1.9.2. Packet Generator Registers 1.9.3. Traffic Monitor Registers
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices

1.7. Testbench

You can use the provided testbench to verify the reference designs. The testbench loops back Ethernet packet into the designs.

Figure 4. Testbench Block Diagram
Table 3.  Testbench Components
Component Description
Device under test (DUT) The reference design.
Avalon driver Consists of Avalon Streaming (Avalon-ST) master bus functional models (BFMs) to generate and monitor ethernet packets. The driver also connects with the design components through the Avalon Memory-Mapped (Avalon-MM) interface.
Ethernet packet monitors Monitor transmit and receive datapaths, and display the frames in the simulator console.

Section Content
Testbench Files
Simulating the Testbench
Test Case: Design With the IEEE 1588v2 Feature
Test Case: Design Without the IEEE 1588v2 Feature

Level Two Title