AN 744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices

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ID 683785
Date 5/13/2016
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Document Table of Contents
Document Table of Contents x
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices x
1.1. Block Diagrams 1.2. Design Components 1.3. Design Parameters 1.4. Hardware and Software Requirements 1.5. Using the Reference Design 1.6. Upgrading the Components 1.7. Testbench 1.8. Interface Signals 1.9. Configuration Registers 1.10. Document Revision History
1.7. Testbench x
1.7.1. Testbench Files 1.7.2. Simulating the Testbench 1.7.3. Test Case: Design With the IEEE 1588v2 Feature 1.7.4. Test Case: Design Without the IEEE 1588v2 Feature
1.8. Interface Signals x
1.8.1. Packet Classifier Interface Signals 1.8.2. ToD Interface Signals
1.9. Configuration Registers x
1.9.1. ToD Registers 1.9.2. Packet Generator Registers 1.9.3. Traffic Monitor Registers
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices

1.5. Using the Reference Design

Follow these steps to start using the reference design:

  1. Unzip the design files in the project directory.
    • altera_eth_tse_wo_1588.tar.gz—the design without the IEEE 1588v2 feature.
    • altera_eth_tse_w_1588.tar.gz—the design with the IEEE 1588v2 feature.
  2. Change to one of the following working directories:
    • altera_eth_tse_wo_1588 if you are using the design without the IEEE 1588v2 feature.
    • altera_eth_tse_w_1588 if you are using the design with the IEEE 1588v2 feature.
  3. Launch the Quartus II software and open the project file, altera_eth_top.qpf.
  4. The default number of channels for the designs is two. To change the number of channels, open the altera_eth_top.sv file and change the value of the NUM_CHANNELS parameter.
  5. Select Processing > Start Compilation to compile the design example.
    You may see a net delay violation at the end of the compilation, which you can ignore. The cause is the violation of a lower boundary in the altera_avalon_mm_clock_crossing bridge module.
  6. Configure the FPGA on the Arria 10 GX SI development board using the generated programming file, altera_eth_top.sof.
  7. When the FPGA is successfully configured, launch the Clock Control tool. The tool's executable—\examples\board_test_system\ClockControl.exe—is shipped with the Installation Kit for the Arria 10 GX SI development board.
  8. Set Y5 to 125 MHz.
    Figure 3. Clock Control
  9. Reset the system by pressing the user push button S1.
  10. In the Quartus II software, select Tool > System Debugging Tools > System Console.
  11. In the System Console command shell, change to the SystemConsole directory.
  12. Initialize the reference design command list by running this command, source main.tcl.
  13. You can now perform the tests listed below. In these tests, the Triple-Speed Ethernet IP core operates in SGMII mode.
    Option Description
    PHY internal serial loopback

    TEST_PHYSERIAL_LOOPBACK <channel_number> <speed_test> <burst_size>

    Example:

    TEST_PHYSERIAL_LOOPBACK 0 1G 1000

    SMA loopback

    TEST_SMA_LOOPBACK <channel_number> <speed_test> <burst_size>

    Example:

    TEST_SMA_LOOPBACK 0 1G 1000

    SPF+ loopback between 2 channels

    TEST_1588 <from_channel> <to_channel> <speed_test>

    Example:

    TEST_1588 0 0 1G

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