AN 744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices

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ID 683785
Date 5/13/2016
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Document Table of Contents
Document Table of Contents x
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices x
1.1. Block Diagrams 1.2. Design Components 1.3. Design Parameters 1.4. Hardware and Software Requirements 1.5. Using the Reference Design 1.6. Upgrading the Components 1.7. Testbench 1.8. Interface Signals 1.9. Configuration Registers 1.10. Document Revision History
1.7. Testbench x
1.7.1. Testbench Files 1.7.2. Simulating the Testbench 1.7.3. Test Case: Design With the IEEE 1588v2 Feature 1.7.4. Test Case: Design Without the IEEE 1588v2 Feature
1.8. Interface Signals x
1.8.1. Packet Classifier Interface Signals 1.8.2. ToD Interface Signals
1.9. Configuration Registers x
1.9.1. ToD Registers 1.9.2. Packet Generator Registers 1.9.3. Traffic Monitor Registers
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices

1.8.2. ToD Interface Signals

Table 7.  ToD Interface SignalsThe Master and Slave ToDs are one of the components in the design with the IEEE 1588v2 feature.
Signal Direction Width Description
master_pulse_per_second Out 1 Pulse per second, the output from the Master PPS module. This signal asserts for 10ms.
start_tod_sync[] In NUM_CHANNELS Assert the respective signal bit to start TOD synchronization process for the channel. The synchronization process continues as long as this signal stays asserted.
pulse_per_second_10g[] Out NUM_CHANNELS Pulse per second for each channel, the output from10G PPS module. This signals asserts for 10ms.
pulse_per_second_1g[] Out NUM_CHANNELS Pulse per second for each channel, the output from1G PPS module. This signals asserts for 10ms.
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