Networking Interface for Open Programmable Acceleration Engine: Intel FPGA Programmable Acceleration Card D5005

Download PDF
ID 683830
Date 11/04/2019
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Overview 3. Partial Reconfiguration HSSI Interface 4. Native PHY IP Core Parameters 5. OPAE Support 6. Document Revision History for Networking Interface for OPAE
1. About this Document x
1.1. Conventions 1.2. Acceleration Glossary
2. Overview x
2.1. Logical View 2.2. Physical View 2.3. Clock Architecture
3. Partial Reconfiguration HSSI Interface x
3.1. Clock Signals 3.2. Data Interface and Signals 3.3. Control and Status Signals 3.4. Connecting the PCS to the HSSI Interface
5. OPAE Support x
5.1. Supported Settings 5.2. Unsupported Settings 5.3. Tuning Information
1. About this Document
2. Overview
3. Partial Reconfiguration HSSI Interface
4. Native PHY IP Core Parameters
5. OPAE Support
6. Document Revision History for Networking Interface for OPAE

3.4. Connecting the PCS to the HSSI Interface

In 32-bit PCS-Direct mode, the interface between the PCS and HSSI PHY maps as following:
Table 8.  Interface Mapping
TX Port Function TX Port RX Port Function RX Port
Configuration-32, PMA Width-32, FPGA Fabric width-32
data[31:0] tx_parallel_data[31:0] data[31:0] rx_parallel_data[31:0]
tx_fifo_wr_en tx_parallel_data[79] rx_prbs_err rx_parallel_data[35]
    rx_prbs_done rx_parallel_data[36]
rx_data_valid rx_parallel_data[79]
Figure 8. Connecting the PCS to the HSSI Interface

This figure illustrates how to connect a 10GbE PCS to the HSSI PHY using the PR HSSI Interface.

Level Two Title