Networking Interface for Open Programmable Acceleration Engine: Intel FPGA Programmable Acceleration Card D5005

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ID 683830
Date 11/04/2019
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Overview 3. Partial Reconfiguration HSSI Interface 4. Native PHY IP Core Parameters 5. OPAE Support 6. Document Revision History for Networking Interface for OPAE
1. About this Document x
1.1. Conventions 1.2. Acceleration Glossary
2. Overview x
2.1. Logical View 2.2. Physical View 2.3. Clock Architecture
3. Partial Reconfiguration HSSI Interface x
3.1. Clock Signals 3.2. Data Interface and Signals 3.3. Control and Status Signals 3.4. Connecting the PCS to the HSSI Interface
5. OPAE Support x
5.1. Supported Settings 5.2. Unsupported Settings 5.3. Tuning Information
1. About this Document
2. Overview
3. Partial Reconfiguration HSSI Interface
4. Native PHY IP Core Parameters
5. OPAE Support
6. Document Revision History for Networking Interface for OPAE

6. Document Revision History for Networking Interface for OPAE

Document Version Acceleration Stack Version Changes
2019.11.04 2.0.1

(compatible with Intel® Quartus® Prime Pro Edition 19.2)

Updated the entire document to reflect:
  • Addition of the PHY PCS-direct mode and hssi_PRBS AFU support.
  • Removal of the 10GbE MAC AFU support.
2019.08.05 2.0

(compatible with Intel® Quartus® Prime Pro Edition 18.1.2)

Initial release.
Level Two Title