Networking Interface for Open Programmable Acceleration Engine: Intel FPGA Programmable Acceleration Card D5005

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ID 683830
Date 11/04/2019
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Overview 3. Partial Reconfiguration HSSI Interface 4. Native PHY IP Core Parameters 5. OPAE Support 6. Document Revision History for Networking Interface for OPAE
1. About this Document x
1.1. Conventions 1.2. Acceleration Glossary
2. Overview x
2.1. Logical View 2.2. Physical View 2.3. Clock Architecture
3. Partial Reconfiguration HSSI Interface x
3.1. Clock Signals 3.2. Data Interface and Signals 3.3. Control and Status Signals 3.4. Connecting the PCS to the HSSI Interface
5. OPAE Support x
5.1. Supported Settings 5.2. Unsupported Settings 5.3. Tuning Information
1. About this Document
2. Overview
3. Partial Reconfiguration HSSI Interface
4. Native PHY IP Core Parameters
5. OPAE Support
6. Document Revision History for Networking Interface for OPAE

4. Native PHY IP Core Parameters

During the FIM instantiation, the following IP parameters were selected for generating the PHY IP core. These parameter settings are informatory, you can not control or configure them. For more information about these parameters, refer to the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide.
Figure 9. Category: General
Figure 10. Category: TX PMA
Figure 11. Category: RX PMA
Figure 12. Category: PCS-Direct
Figure 13. Category: PCS Core Interface
Figure 14. Category: Analog PMA Setting
Figure 15. Category: ATX PLL IP Setting
Figure 16. Category: fPLL IP Setting
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