Networking Interface for Open Programmable Acceleration Engine: Intel FPGA Programmable Acceleration Card D5005

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ID 683830
Date 11/04/2019
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Overview 3. Partial Reconfiguration HSSI Interface 4. Native PHY IP Core Parameters 5. OPAE Support 6. Document Revision History for Networking Interface for OPAE
1. About this Document x
1.1. Conventions 1.2. Acceleration Glossary
2. Overview x
2.1. Logical View 2.2. Physical View 2.3. Clock Architecture
3. Partial Reconfiguration HSSI Interface x
3.1. Clock Signals 3.2. Data Interface and Signals 3.3. Control and Status Signals 3.4. Connecting the PCS to the HSSI Interface
5. OPAE Support x
5.1. Supported Settings 5.2. Unsupported Settings 5.3. Tuning Information
1. About this Document
2. Overview
3. Partial Reconfiguration HSSI Interface
4. Native PHY IP Core Parameters
5. OPAE Support
6. Document Revision History for Networking Interface for OPAE

3.3. Control and Status Signals

The PR HSSI Interface provides signals for HSSI PHY PCS status and transceiver loopback control. The signal behavior conforms to the Intel® Stratix® 10 FPGA Transceiver Native PHY IP core in 32-bit PCS-Direct mode. The below table cross references the HSSI port names to the Native PHY IP port names.
Table 7.  Control and Status Signals
hssi Port Name Width Direction Clock Domain Native PHY IP Core

Port Name

 Reference
f2a_tx_ready 4 Output Reserved
f2a_rx_ready 4 Output Reserved
a2f_rx_seriallpbken 4 Input Asynchronous rx_seriallpbken Table: RX PMA Ports-PMA QPI Options in PMA, Calibration, and Reset Ports
f2a_atxpll_locked 1 Output Asynchronous - -
f2a_fpll_locked 1 Output Asynchronous - -
f2a_tx_cal_busy 4 Output Asynchronous tx_cal_busy Table: User-coded Reset Controller, Transceiver PHY, and TX PLL Signals in User-Coded Reset Controller Signals
f2a_rx_cal_busy 4 Output Asynchronous rx_cal_busy Table: User-coded Reset Controller, Transceiver PHY, and TX PLL Signals in User-Coded Reset Controller Signals
f2a_rx_is_lockedtodata 4 Output Synchronous to CDR rx_is_lockedtodata
f2a_rx_is_lockedtoref 4 Output f2a_rx_clkout[n] rx_is_lockedtoref Table: RX PMA Ports in PMA, Calibration, and Reset Ports
a2f_tx_analogreset 4 Input Synchronous to Reset Controller IP input clock (recommended 100-125MHz) tx_analogreset Table: User-coded Reset Controller, Transceiver PHY, and TX PLL Signals in User-Coded Reset Controller Signals
a2f_rx_analogreset 4 Input Synchronous to the Reset Controller IP core input clock (recommended 100-125MHz) rx_analogreset Table: User-coded Reset Controller, Transceiver PHY, and TX PLL Signals in User-Coded Reset Controller Signals
f2a_tx_analogreset_stat 4 Output Asynchronous tx_analogreset_stat
f2a_rx_analogreset_stat 4 Output Asynchronous rx_analogreset_stat
a2f_tx_digitalreset 4 Input Synchronous to the Reset Controller IP core input clock (recommended 100-125MHz) tx_digitalreset
a2f_rx_digitalreset 4 Input Synchronous to the Reset Controller IP core input clock (recommended 100-125MHz) rx_digitalreset
f2a_tx_digitalreset_stat 4 Output Asynchronous tx_digitalreset_stat
f2a_rx_digitalreset_stat 4 Output Asynchronous rx_digitalreset_stat
Level Two Title