Intel® Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 9/08/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.3.2.2. Connecting the IOPLL and IOPLL Reconfig IP Cores

To connect the IOPLL and IOPLL Reconfig IP cores in your design, follow these steps:

  1. Connect the reconfig_to_pll[29..0] bus on the IOPLL Reconfig IP core to the reconfig_to_pll[29..0] bus on the IOPLL IP core.
  2. Connect the reconfig_from_pll[10..0] bus on the IOPLL Reconfig IP core to the reconfig_from_pll[10..0] bus on the IOPLL IP core.
  3. Connect the mgmt_clk port to a valid clock source.
  4. Connect the mgmt_reset port, mgmt_waitrequest port, mgmt_read port, mgmt_write port, mgmt_readdata[7..0] bus, mgmt_writedata[7..0] bus, and mgmt_address[9..0] bus to user control logic to perform read and write operations.