Intel® Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 9/08/2023
Public

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7.2.2. Output Clock and the Corresponding Data Bit Setting for Clock Gating Reconfiguration

Table 25.  Output Clock and the Corresponding Data Bit Setting for Clock Gating Reconfiguration
Output Clock Data Bus Bit Setting (Binary)
C0 data[0]

Gated = 1'b0

Ungated = 1'b1

C1 data[1]
C2 data[2]
C3 data[3]
C4 data[4]
C5 data[5]
C6 data[6]
C7 data[7]