ALTDQ_DQS2 IP Core User Guide

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ID 683742
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
ALTDQ_DQS2 IP Core User Guide
ALTDQ_DQS2 IP Core User Guide x
ALTDQ_DQS2 Features ALTDQ_DQS2 Device Support Resource Utilization and Performance ALTDQ_DQS2 Parameter Settings ALTDQ_DQS2 Data Paths ALTDQ_DQS2 Ports Dynamic Reconfiguration for ALTDQ_DQS2 Stratix V Design Example Arria V Design Example IP-Generate Command ALTDQ_DQS2 IP Core User Guide Archives Document Revision History
ALTDQ_DQS2 Data Paths x
DQ and DQS Input Path DQ and DQS Output Path
DQ and DQS Input Path x
DQ and DQS Input Paths for Stratix V Devices Data Input Path for Arria V, Cyclone V, and Stratix V Devices Blocks in DQ and DQS Data Input Path
Blocks in DQ and DQS Data Input Path x
DQS Logic Capture DDIO to Read FIFO Path FIFO Control
DQ and DQS Output Path x
DQ and DQS Output Path for Stratix V Devices Blocks in DQ and DQS Output Path DQ and DQS Output Path for Arria V and Cyclone V Devices
ALTDQ_DQS2 Ports x
ALTDQ_DQS2 Data Strobe Ports ALTDQ_DQS2 Data Ports ALTDQ_DQS2 Termination Control Ports ALTDQ_DQS2 PLL and DLL Ports ALTDQ_DQS2 Hard FIFO Ports ALTDQ_DQS2 Dynamic Configuration Ports
Dynamic Reconfiguration for ALTDQ_DQS2 x
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2
Stratix V Design Example x
Instantiating ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Stratix V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Stratix V Design Example x
Dynamic Configuration SDC Walkthrough
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results
DQS Read Operation x
DQS Delay Chain Hard Read FIFO
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe
Arria V Design Example x
Instantiating the ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Arria V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Arria V Design Example x
Dynamic Configuration
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results SDC Walkthrough
DQS Read Operation x
DQS Delay Chain VFIFO, LFIFO, and Read FIFO DQS Enable Control
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe Timing Violation tq_analysis.tcl
IP-Generate Command x
Using IP-Generate Command
ALTDQ_DQS2 IP Core User Guide

ALTDQ_DQS2 Hard FIFO Ports

Hard FIFO Ports

Ports

Type

Width

Description

lfifo_rdata_en_full

Input

2

Data input to the latency shifter FIFO. This signal is the full read enable token generated by user logic and is asserted for the length of the desired read burst. This token is delayed by a variable number of integer cycles inside the latency shifter FIFO and used to feed the read enable signal of the read FIFO.

This port is only supported in Arria V and Cyclone V devices.

lfifo_rden Input

1

Data input to the Read FIFO Read Enable. This signal is the full read enable token generated by user logic and is asserted for the length of the desired read burst.

This port is only supported in Stratix V devices.

lfifo_reset_n

Input

1

Active high reset to the latency shifter FIFO

This port is only supported in Arria V and Cyclone V devices.

lfifo_rd_latency[]

Input

5

The number of cycles to delay data inputs feeding the latency shifter FIFO. A maximum of 31 cycles is supported.

This port is only supported in Arria V and Cyclone V devices.

vfifo_qvld

Input

Arria V and Cyclone V devices: 2

Stratix V devices: 1

Data input to the data valid FIFO. This signal is the full read enable token generated by user logic and is asserted for the length of the desired read burst. This signal is driven by the same user logic that drives the lfifo_rdata_en_full signal.

In general applications, you can leave this port unconnected.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

vfifo_inc_wr_ptr

Input

2

Increments the latency implemented by the data valid FIFO by one cycle.

This port is only supported in Arria V and Cyclone V devices.

vfifo_reset_n

Input

1

Active high reset to the data valid FIFO

This port is only supported in Arria V and Cyclone V devices.

rfifo_reset_n

Input

1

Active high reset to the read FIFO .

This port is only supported in Arria V and Cyclone V devices.

The I/O and DQS configuration blocks represent a set of serial-to-parallel shift registers that dynamically changes the settings of various device configuration bits. The I/O and DQS configuration blocks shift a serial configuration data stream into the shift registers, and then load the data stream into the configuration registers. The shift registers power-up low. Every I/O pin contains an I/O configuration block. Every DQS group contains a DQS configuration block and an I/O configuration block.

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