ALTDQ_DQS2 IP Core User Guide

Download PDF
ID 683742
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
ALTDQ_DQS2 IP Core User Guide
ALTDQ_DQS2 IP Core User Guide x
ALTDQ_DQS2 Features ALTDQ_DQS2 Device Support Resource Utilization and Performance ALTDQ_DQS2 Parameter Settings ALTDQ_DQS2 Data Paths ALTDQ_DQS2 Ports Dynamic Reconfiguration for ALTDQ_DQS2 Stratix V Design Example Arria V Design Example IP-Generate Command ALTDQ_DQS2 IP Core User Guide Archives Document Revision History
ALTDQ_DQS2 Data Paths x
DQ and DQS Input Path DQ and DQS Output Path
DQ and DQS Input Path x
DQ and DQS Input Paths for Stratix V Devices Data Input Path for Arria V, Cyclone V, and Stratix V Devices Blocks in DQ and DQS Data Input Path
Blocks in DQ and DQS Data Input Path x
DQS Logic Capture DDIO to Read FIFO Path FIFO Control
DQ and DQS Output Path x
DQ and DQS Output Path for Stratix V Devices Blocks in DQ and DQS Output Path DQ and DQS Output Path for Arria V and Cyclone V Devices
ALTDQ_DQS2 Ports x
ALTDQ_DQS2 Data Strobe Ports ALTDQ_DQS2 Data Ports ALTDQ_DQS2 Termination Control Ports ALTDQ_DQS2 PLL and DLL Ports ALTDQ_DQS2 Hard FIFO Ports ALTDQ_DQS2 Dynamic Configuration Ports
Dynamic Reconfiguration for ALTDQ_DQS2 x
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2
Stratix V Design Example x
Instantiating ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Stratix V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Stratix V Design Example x
Dynamic Configuration SDC Walkthrough
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results
DQS Read Operation x
DQS Delay Chain Hard Read FIFO
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe
Arria V Design Example x
Instantiating the ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Arria V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Arria V Design Example x
Dynamic Configuration
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results SDC Walkthrough
DQS Read Operation x
DQS Delay Chain VFIFO, LFIFO, and Read FIFO DQS Enable Control
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe Timing Violation tq_analysis.tcl
IP-Generate Command x
Using IP-Generate Command
ALTDQ_DQS2 IP Core User Guide

I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices

Figure 7. I/O and DQS Delay Chains for Arria V GZ and Stratix V Devices


The following tables lists the I/O configuration block bit sequence, description, and settings for Arria V GZ and Stratix V devices.

Table 2.  I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices

Legend in Figure 7

Bit

Bit Name

Description

A

5..0

padtoinputregisterdelaysetting

Connects to the delayctrlin port of the D1 delay chain to control the first I/O buffer‑to-input register delay chain (D1).

Sets to tune the DQ delay (read calibration) for DDR applications.

For delay values, refer to the “Programmable IOE Delay” section in the Stratix V Device Datasheet.

B

11..6

padtoinputregisterrisefalldelaysetting

Connects to the delayctrlin port of the second D1 delay chain to control the second pad‑to‑input register delay chain (D1).

For delay values, refer to the “Programmable IOE Delay” section in the Stratix V Device Datasheet.

C

17..12

outputdelaysetting1

Connects to the delayctrlin port of the D5 delay chain to control the output register‑to‑I/O buffer delay chain (D5) in the output path and output enable paths.

This delay is for write calibration for DDR application.

For delay values, refer to the “Programmable IOE Delay” section in the Stratix V Device Datasheet.

D

23..18

outputdelaysetting2

Connects to the delayctrlin port of the second D5 delay chain to control the output register-to-I/O buffer delay chain (second D5) in the output path and output enable paths.

This delay is for write calibration for DDR application.

For delay values, refer to the “Programmable IOE Delay” section in the Stratix V Device Datasheet.

—

39..24

inputclkndelaysetting

inputclkdelaysetting

dutycycledelaymode

dutycycledelaysetting

Unconfigurable bits.

Always set bits to its default value.

Table 3.  I/O Configuration Block Bit Value for Arria V GZ and Stratix V Devices
Bit

Bit Name/

Bit

Default Value (Binary)

Min. Value

Max. Value

Inc. Value

5..0

padtoinputregisterdelaysetting

000000

intrinsic delay

787.5 ps + intrinsic delay

12.5 ps

11..6

padtoinputregisterrisefalldelaysetting

000000

intrinsic delay

787.5 ps + intrinsic delay

12.5 ps

17..12

outputdelaysetting1

000000

intrinsic delay

787.5 ps + intrinsic delay

12.5 ps

23..18

outputdelaysetting2

000000

intrinsic delay

787.5 ps + intrinsic delay

12.5 ps

39..24

inputclkndelaysetting

inputclkdelaysetting

dutycycledelaymode

dutycycledelaysetting

0000000000000000

—

—

—

Related Information
Level Two Title