ALTDQ_DQS2 IP Core User Guide

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ID 683742
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
ALTDQ_DQS2 IP Core User Guide
ALTDQ_DQS2 IP Core User Guide x
ALTDQ_DQS2 Features ALTDQ_DQS2 Device Support Resource Utilization and Performance ALTDQ_DQS2 Parameter Settings ALTDQ_DQS2 Data Paths ALTDQ_DQS2 Ports Dynamic Reconfiguration for ALTDQ_DQS2 Stratix V Design Example Arria V Design Example IP-Generate Command ALTDQ_DQS2 IP Core User Guide Archives Document Revision History
ALTDQ_DQS2 Data Paths x
DQ and DQS Input Path DQ and DQS Output Path
DQ and DQS Input Path x
DQ and DQS Input Paths for Stratix V Devices Data Input Path for Arria V, Cyclone V, and Stratix V Devices Blocks in DQ and DQS Data Input Path
Blocks in DQ and DQS Data Input Path x
DQS Logic Capture DDIO to Read FIFO Path FIFO Control
DQ and DQS Output Path x
DQ and DQS Output Path for Stratix V Devices Blocks in DQ and DQS Output Path DQ and DQS Output Path for Arria V and Cyclone V Devices
ALTDQ_DQS2 Ports x
ALTDQ_DQS2 Data Strobe Ports ALTDQ_DQS2 Data Ports ALTDQ_DQS2 Termination Control Ports ALTDQ_DQS2 PLL and DLL Ports ALTDQ_DQS2 Hard FIFO Ports ALTDQ_DQS2 Dynamic Configuration Ports
Dynamic Reconfiguration for ALTDQ_DQS2 x
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2
Stratix V Design Example x
Instantiating ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Stratix V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Stratix V Design Example x
Dynamic Configuration SDC Walkthrough
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results
DQS Read Operation x
DQS Delay Chain Hard Read FIFO
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe
Arria V Design Example x
Instantiating the ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Arria V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Arria V Design Example x
Dynamic Configuration
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results SDC Walkthrough
DQS Read Operation x
DQS Delay Chain VFIFO, LFIFO, and Read FIFO DQS Enable Control
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe Timing Violation tq_analysis.tcl
IP-Generate Command x
Using IP-Generate Command
ALTDQ_DQS2 IP Core User Guide

ALTDQ_DQS2 Parameter Settings

You can instantiate and parameterize using the IP Catalog and parameter editor GUI, or the ip-generate command through the command-line interface (CLI).

The following table lists the ALTDQ_DQS2 parameter settings.

Table 1.  ALTDQ_DQS2 Parameter Settings

Parameter Editor GUI Setting

CLI Parameter Description

Name

Legal Values

Name

Legal Values 1
General Settings

Pin width

1 to 36

PIN_WIDTH 1 to 36

This setting specifies the number of data (DQ) pins to make as part of this DQS group.

The default value is 9.

Cyclone V devices support only x8/x9 DQ/DQS groups. The maximum number of pins including strobes is 12.

Pin type

input

output

bidir

PIN_TYPE

input

output

bidir

This setting specifies the direction of the data pins (input, output, or bidirectional).

The default value is bidir (bidir).

Extra output-only pins

0 – 36

EXTRA_OUTPUT_WIDTH 0 to 36

This setting specifies the extra output pins that you need as part of a DQS group.

A common use for this setting is to add datamask pins.

The default value is 0 (0).

Memory frequency

1–1068

INPUT_FREQ 120–1068

This setting specifies the full-rate clock frequency of the incoming DQS group signal from the external device in MHz.

The default value is 300 MHz (300).

Use DLL Offset Control

—

USE_OFFSET_CTRL

true

false

This setting enables dynamic control of the DLL offset.

Altera recommends using this setting for test purposes only. For DQS data capture calibration, use the D1, D2, D3, and D4 delay chains.

Enable hard FIFOs

—

USE_HARD_FIFOS

true

false

This setting enables the hard FIFOs (read FIFO for Stratix V devices and read FIFO, latency shifter FIFO and data valid FIFO for Arria V and Cyclone V devices) as part of the ALTDQ_DQS2 IP core.

Use Capture Clock to clock the read Side of the Hard VFIFO

—

USE_DQSIN_FOR_VFIFO_READ

true

false

Turn on this setting when you use the hard data valid FIFO and when the capture clock is not gated.

This setting is available only for Arria V and Cyclone V devices.

Enable dual write clocks

—

DUAL_WRITE_CLOCK

true

false

This setting enables the use of separate output clocks for data and strobe.

This setting is disabled by default for Arria V and Cyclone V devices.

Use dynamic configuration scan chains

—

USE_DYNAMIC_CONFIG

true

false

This setting enables run‑time configuration of multiple delay chains, phase shifts, and transfer registers.

Requires a correctly formatted bitstream.

For more information, refer to DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices and DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices.

Output Path

Use half-rate output path

—

HALF_RATE_OUTPUT

true

false

This setting doubles the width of the data bus on the FPGA side and clocks the FPGA side interface using the half‑rate clock input.

If this setting is enabled, drive the hr_clock_in port with the half‑rate clock signal.

When enabling hard read FIFO in a Stratix V device, you must set this parameter to true.

This setting is enabled by default.

Use output phase alignment blocks

—

USE_OUTPUT_PHASE_ALIGNMENT

true

false

This setting enables phase shift on the output path based on the delay settings from the DLL.

This setting is disabled by default.

Capture Strobe

Capture strobe type

Single

Differential

Complementary

CAPTURE_STROBE_TYPE

single

differential

complementary

This setting specifies the type of capture strobe (DQS signal from the external device).

The default value is Single (single).

Use inverted capture strobe

—

INVERT_CAPTURE_STROBE

true

false

When enabled, this parameter captures data with an inverted capture strobe.

Strobe inversion occurs from dqsbusout (an output port from the DQS delay chain block) to the clock input of the DDIO_IN block.

This setting is enabled by default.

DQS phase shift

0 degrees

45 degrees

90 degrees

135 degrees

DQS_PHASE_SETTING

0

1

2

3

This setting specifies the phase shift value for the DQS delay chain to shift the incoming strobe in the data valid window during read and write operations.

The default value is 90 degrees (2).

Arria V and Cyclone V devices support only 0 and 90 degrees.

Use capture strobe enable block 2

—

USE_DQS_ENABLE

true

false

This setting enables the capture strobe enable block, which allows control over the preamble state of the capture strobe.

This setting is disabled by default.

This setting is available for Arria V GZ and Stratix V devices only.

Treat the capture strobe enable as a half-rate signal

—

USE_HALF_RATE_DQS_ENABLE

true

false

This setting doubles the width of the capture strobe enable bus on the FPGA side and clocks the FPGA side interface using the half-rate clock input.

DQS enable phase setting

0 degrees

45 degrees

90 degrees

135 degrees

DQS_ENABLE_PHASE_SETTING

0

1

2

3

This setting specifies the value of phase shift to shift the full-rate clock signal that drives the capture strobe enable block.

The default value is 0 degrees (0).

Output Strobe

Generate output strobe

—

USE_OUTPUT_STROBE

true

false

This setting generates an output strobe signal based on the OE signal and the full-rate clock. This setting is enabled by default.

Make capture strobe bidirectional 3 4

—

USE_BIDIR_STROBE

true

false

This setting enables the bidirectional capture strobe (capture strobe and output strobe is on the same port).

This setting is disabled by default.

Differential/ complementary output strobe

—

DIFFERENTIAL_OUTPUT_STROBE

true

false

This setting enables either the differential or complementary output strobe.

This setting is disabled by default.

Use reset signal to stop output strobe

—

USE_OUTPUT_STROBE_RESET

true

false

This setting stops the unidirectional output strobe using a user-provided reset signal. The core_clock_in and the reset_n_core_clock_in signals are required.

OCT Source

Output Strobe Enable

Data Write Enable

Dedicated OCT Enable

OCT_SOURCE

0

1

2

This setting specifies the type of input signal to toggle the OCT control:

  • Output Strobe Enable—Uses the output_strobe_ena input as the OCT control signal.
  • Data Write Enable—Uses the write_oe_in input as the OCT control signal.
  • Dedicated OCT Enable—Adds a oct_ena_in input to the interface, which is used as the OCT control signal.

The availability of the Output Strobe Enable, Data Write Enable,and Dedicated OCT Enable are dependent on PIN_TYPE and USE_BIDIR_STROBE parameters.

Default value is Data Write Enable.

Preamble type

high

low

none

PREAMBLE_TYPE

high

low

none

This setting sets the DQS preamble to high (DDR3), low (DDR2), or none:

  • When you select low and the strobe is bidirectional, the output strobe is held low for the first full rate cycle.
  • When you select high or none, the strobe is driven high for the first full rate cycle.
  • Default value is low.
Note: The ALTDQ_DQS2 IP core does not support DQS tracking.
Related Information
1 All CLI parameter values are type string, therefore you must enclose the values in double quotes.
2 Refer to KDB Link if Use capture strobe enable block and Make capture strobe bidirectional parameters are enabled.
3 For Arria V GZ and Stratix V devices, please refer to KDB Link if Use capture strobe enable block and Make capture strobe bidirectional parameters are enabled.
4 For Arria V (except GZ) and Cyclone V devices, please refer to KDB Link if the parameter is enabled.
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