ALTDQ_DQS2 IP Core User Guide

Download PDF
ID 683742
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
ALTDQ_DQS2 IP Core User Guide
ALTDQ_DQS2 IP Core User Guide x
ALTDQ_DQS2 Features ALTDQ_DQS2 Device Support Resource Utilization and Performance ALTDQ_DQS2 Parameter Settings ALTDQ_DQS2 Data Paths ALTDQ_DQS2 Ports Dynamic Reconfiguration for ALTDQ_DQS2 Stratix V Design Example Arria V Design Example IP-Generate Command ALTDQ_DQS2 IP Core User Guide Archives Document Revision History
ALTDQ_DQS2 Data Paths x
DQ and DQS Input Path DQ and DQS Output Path
DQ and DQS Input Path x
DQ and DQS Input Paths for Stratix V Devices Data Input Path for Arria V, Cyclone V, and Stratix V Devices Blocks in DQ and DQS Data Input Path
Blocks in DQ and DQS Data Input Path x
DQS Logic Capture DDIO to Read FIFO Path FIFO Control
DQ and DQS Output Path x
DQ and DQS Output Path for Stratix V Devices Blocks in DQ and DQS Output Path DQ and DQS Output Path for Arria V and Cyclone V Devices
ALTDQ_DQS2 Ports x
ALTDQ_DQS2 Data Strobe Ports ALTDQ_DQS2 Data Ports ALTDQ_DQS2 Termination Control Ports ALTDQ_DQS2 PLL and DLL Ports ALTDQ_DQS2 Hard FIFO Ports ALTDQ_DQS2 Dynamic Configuration Ports
Dynamic Reconfiguration for ALTDQ_DQS2 x
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2
Stratix V Design Example x
Instantiating ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Stratix V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Stratix V Design Example x
Dynamic Configuration SDC Walkthrough
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results
DQS Read Operation x
DQS Delay Chain Hard Read FIFO
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe
Arria V Design Example x
Instantiating the ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Arria V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Arria V Design Example x
Dynamic Configuration
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results SDC Walkthrough
DQS Read Operation x
DQS Delay Chain VFIFO, LFIFO, and Read FIFO DQS Enable Control
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe Timing Violation tq_analysis.tcl
IP-Generate Command x
Using IP-Generate Command
ALTDQ_DQS2 IP Core User Guide

DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices

The following tables lists the DQS configuration block bit sequence, description, and settings for Arria V and Cyclone V devices.

Table 8.  DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices

Legend in Figure 1

Bit

Bit Name

Description

G

4..0

dqsenableungatingdelaysetting

Connects to the delayctrlin port of postamble T11 delay chain (ungated). Aligns the postamble signal in terms of DQS signal by selecting different delays.

H

9..5

dqsenablegatingdelaysetting

Connects to the delayctrlin port of the postamble T11 delay chain (gated). Aligns the postamble signal in terms of DQS signal by selecting different delays.

I

10

enadqsenablephasetransferreg

Connects to the enaphasetransferreg port of the DQS Enable Control block to allow an additional negative edge- triggered register to be added to the DQS enable control path to satisfy the setup or hold time requirement for the phase transfer.

J

15..11

octdelaysetting

Connects to the delayctrlin port of the D5 delay chain.

Controls the dynamic OCT output register-to-I/O buffer delay chain (D5).

For delay values, refer to the “Programmable IOE Delay” sections in the Arria V Device Datasheet and the Cyclone V Device Datasheet, respectively.

K

16

dqshalfratebypass

Sets the multiplexers in the DQS enable logic, OCT logic, and FIFO control logic to dynamically switch from half-rate to full-rate configuration.

L

21..17

dqsbusoutdelaysetting

Connects to the delayctrlin port of the read DQS D4 delay chain. Controls the delay tuning of the DQS signal feeding into the DQS bus.

M

22

postamblephaseinvert

Connects to the phaseinvertctrl port of the clock phase select block to select between the non-inverted and inverted output. This clock phase select block is used to level the postamble clock (in leveling multiplexer). This setting allows the phase output from the delay chain to be inverted to gain additional phases.

N

24..23

postamblephasesetting

Connects to the phasectrlin port of the clock phase select block to select between phase shifts of 0°, 45°, 90°, and 135°. This particular clock phase select block is used to level the postamble clock (in leveling multiplexer).

—

29..25

Not mapped to any port

Unconfigurable bits. Always set bits to its default value.

Table 9.  DQS Configuration Block Bit Value for Arria V and Cyclone V Devices

Bit

External Bit Name

Default Value (Binary)

Min. Value

Max. Value

Inc. Value

4..0

dqsenableungatingdelaysetting

0

intrinsic delay

775 ps + intrinsic delay

25 ps

9..5

dqsenablegatingdelaysetting

0

intrinsic delay

775 ps + intrinsic delay

25 ps

10

enadqsenablephasetransferreg

0

0: Disable Neg-Edge Register

1: Enable Neg-Edge Register

15..11

octdelaysetting

0

intrinsic delay

775 ps + intrinsic delay

25 ps

16

dqshalfratebypass

0

0: Engage Half-Rate Register

1: Bypass Half-Rate Register

21..17

dqsbusoutdelaysetting

0

intrinsic delay

775 ps + intrinsic delay

25 ps

22

postamblephaseinvert

0

0 = Non-invert

1 = Invert

24..23

postamblephasesetting

0

00 = 0°

01 = 45°

10 = 90°

11 = 135°

29..25

Not mapped to any port

0

—

Related Information
Level Two Title