ALTDQ_DQS2 IP Core User Guide

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ID 683742
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
ALTDQ_DQS2 IP Core User Guide
ALTDQ_DQS2 IP Core User Guide x
ALTDQ_DQS2 Features ALTDQ_DQS2 Device Support Resource Utilization and Performance ALTDQ_DQS2 Parameter Settings ALTDQ_DQS2 Data Paths ALTDQ_DQS2 Ports Dynamic Reconfiguration for ALTDQ_DQS2 Stratix V Design Example Arria V Design Example IP-Generate Command ALTDQ_DQS2 IP Core User Guide Archives Document Revision History
ALTDQ_DQS2 Data Paths x
DQ and DQS Input Path DQ and DQS Output Path
DQ and DQS Input Path x
DQ and DQS Input Paths for Stratix V Devices Data Input Path for Arria V, Cyclone V, and Stratix V Devices Blocks in DQ and DQS Data Input Path
Blocks in DQ and DQS Data Input Path x
DQS Logic Capture DDIO to Read FIFO Path FIFO Control
DQ and DQS Output Path x
DQ and DQS Output Path for Stratix V Devices Blocks in DQ and DQS Output Path DQ and DQS Output Path for Arria V and Cyclone V Devices
ALTDQ_DQS2 Ports x
ALTDQ_DQS2 Data Strobe Ports ALTDQ_DQS2 Data Ports ALTDQ_DQS2 Termination Control Ports ALTDQ_DQS2 PLL and DLL Ports ALTDQ_DQS2 Hard FIFO Ports ALTDQ_DQS2 Dynamic Configuration Ports
Dynamic Reconfiguration for ALTDQ_DQS2 x
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2
Stratix V Design Example x
Instantiating ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Stratix V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Stratix V Design Example x
Dynamic Configuration SDC Walkthrough
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results
DQS Read Operation x
DQS Delay Chain Hard Read FIFO
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe
Arria V Design Example x
Instantiating the ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Arria V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Arria V Design Example x
Dynamic Configuration
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results SDC Walkthrough
DQS Read Operation x
DQS Delay Chain VFIFO, LFIFO, and Read FIFO DQS Enable Control
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe Timing Violation tq_analysis.tcl
IP-Generate Command x
Using IP-Generate Command
ALTDQ_DQS2 IP Core User Guide

VFIFO, LFIFO, and Read FIFO

In Arria V and Cyclone V devices, the data valid FIFO (VFIFO) generates the input signal to the DQS_ENABLE_CTRL block and connects to the write enable port of the read FIFO. The latency shifter FIFO (LFIFO) connects to the read enable port of the read FIFO. The LFIFO and VFIFO implement each configurable latencies to determine the time to read enable and write enable for the Read FIFO respectively. The lfifo_rd_latency signal determines the latency setting in the LFIFO while the vfifo_inc_wr_ptr signal determines the latency setting for the VFIFO. The read FIFO is in every input data paths, and you can set the read FIFO to control the conversion between FR-FR or FR-HR in Arria V and Cyclone V devices.

Figure 41. VFIFO, LFIFO and Read FIFO in Arria V and Cyclone V Devices


When the host sends out a read command, a token is also sent to the LFIFO and the VFIFO. This token should be asserted for the length of the desired read burst. This token is referred to lfifo_rdata_en_full (for LFIFO) and vfifo_qvld (for VFIFO). In this testbench, the lfifo_rd_latency is set to 15d. Note that this is consistent with the latency noticed between rdataenfull of the LFIFO and readenable of the read FIFO, which is 16 half- rate clock cycles. The lfifo_rdata_en_full and vfifo_qvld signals pass through each HR-FR DDIO before it reaches the rdataenfull of the LFIFO and the qvldin of the VFIFO at 9.355 ms. The delayed qvldreg of the VFIFO (1.5 half-rate cycles) feeds the DQSENABLEIN of the DQS_ENABLE_CTRL block. Meanwhile, the rden signal of the LFIFO, which is delayed by 16 half-rate cycles, feeds the READENABLE of the read FIFO.

The dqsenable signal is asserted at 9.3825 ms. Edge-aligned input data starts at 9.385 ms and ends at 9.445 ms. The dqsenable signal is deasserted at 9.44 ms. In an actual application, you are required to have some form of DQS enable runtime calibration to obtain the correct DQS gating-ungating window. The strobe_io signal goes to Hi-Z when the DQS read operation completes. Because the writeenable signal of the read FIFO is always asserted, data is written into the read FIFO whenever the read FIFO is available, which is as early as 9.395 ms. However, data is only read out when the readenable signal is asserted between 9.515 ms and 9.575 ms. The data are available in the read_data_out signal. You can further optimize the timing to read the read FIFO by adjusting the LFIFO latency delay to create sufficient space between the read and write pointers in the read FIFO to maximize the throughput.

Figure 42. FIFO Read Waveform


Note: The write enable (we) and read enable (re) signals of the hard read FIFO are different from the wrreq and rdreq signals of the DCFIFO. In DCFIFO, the data are only available at the FIFO output ports when the rdreq signal is asserted. In hard read FIFO, the we signal controls when to advance the write address counter while the re signal controls when to advance the read address counter. When the read and write address pointers are the same, write data appear at the read port as soon as a write operation is completed. This explains why we see the first written data available almost immediately at the FIFO output port. When the signal is asserted, it will advance to the next read address, and then only the second written data is available at the FIFO output port.
Note: Beginning from the Quartus® Prime software version 13.1, the lfifo_rdata_en and lfifo_rdata_valid signals will be removed.
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