AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3.10. Generation of Device Programming Files

Similar to the Hardware Manager in the AMD* Xilinx* Vivado* software, the Assembler in the Intel® Quartus® Prime Pro Edition software generates files that the Programmer can use to program or configure a device with Intel® FPGA programming hardware.
Table 21.  Methods to Generate Programming Files Comparison
GUI Feature AMD* Xilinx* Vivado* Software Intel® Quartus® Prime Pro Edition Software
Generation of Device Programming Files Hardware Manager Assembler

Features

The Assembler converts the Fitter’s device, logic cell, and pin assignments into a programming image for the device, in the form of one or more Programmer Object Files (.pof) or SRAM Object Files (.sof) for the target device. You use a .sof file to program Intel® FPGA devices and a .pof file to configure Intel® FPGA CPLD devices.

Assembler is a stage of the Intel® Quartus® Prime Pro Edition full compilation flow. You can also run Assembler separately, by clicking Processing > Start > Start Assembler.