AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023
Public

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4.3.3. Timing Constraints

You can convert constraints defined in XDC files to SDC commands that the Intel® Quartus® Prime Pro Edition Timing Analyzer can use.

The following table summarizes the most common Vivado* XDC timing constraints and the equivalent SDC timing constraints. You can set the constraints by either modifying the .sdc file or by using the Timing Analyzer GUI.

Table 61.   Vivado* XDC versus Timing Analyzer SDC Timing Constraints
Vivado* XDC Timing Constraint Timing Analyzer SDC Command Description
create_clock

create_generated_clock

set_max_delay

set_false_path

Defines all the clocks and their relationship in a design.
NA derive_pll_clocks Automatically creates a generated clock constraint on each output of the PLLs in a design.
Note: Only Intel® Arria® 10and Intel® Cyclone® 10 GX devices support this command.

For Intel® Stratix® 10 and Intel Agilex® 7 devices, the Timing Analyzer derives PLL clocks from the constraints bound to the related IP.

Vivado* tools auto-derive the generated clocks; therefore, XDC files do not require these constraints.

NA derive_clock_uncertainty Calculates clock-to-clock uncertainties within the FPGA due to characteristics like PLL jitter, clock tree jitter, etc. The Timing Analyzer generates a warning if the command is not present in the SDC files.

Vivado* tools auto-derive the generated clocks; therefore, XDC files do not require these constraints.

set_input_delay Input timing constraint that you use to define the Pad-to-Setup timing requirement in a design.
set_output_delay Defines the global Clock to Pad timing requirement in a design.
set_max_delay Combinational path that constrains all combinational pin to pin paths.
set_false_path Eliminates the paths from timing consideration during Place and Route and timing analysis.
set_clock_groups Cuts timing between clocks in different groups.

For more information about using the SDC commands and their usage, refer to the Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer .